Features Array•Single 2.7V - 3.6V Supply
•Serial Peripheral Interface (SPI) Compatible
–Supports SPI Modes 0 and 3
•70 MHz Maximum Operating Frequency
–Clock-to-Output (t V) of 6 ns Maximum
•Flexible, Optimized Era Architecture for Code + Data Storage Applications –Uniform 4-Kbyte Block Era爱丽丝漫游奇境记作者
–Uniform 32-Kbyte Block Era
–Full Chip Era
•Hardware Controlled Locking of Protected Sectors via WP Pin
•128-Byte Programmable OTP Security Register
•Flexible Programming
–Byte/Page Program (1 to 256 Bytes)
•Fast Program and Era Times
–2.5 ms Typical Page Program (256 Bytes) Time
–100 ms Typical 4-Kbyte Block Era Time
–500 ms Typical 32-Kbyte Block Era Time
•Automatic Checking and Reporting of Era/Program Failures
•JEDEC Standard Manufacturer and Device ID Read Methodology
•Low Power Dissipation
–6 mA Active Read Current (Typical at 20 MHz)
–5 µA Deep Power-Down Current (Typical)
•Endurance: 100,000 Program/Era Cycles
•Data Retention: 20 Years
垃圾分类活动简报•Complies with Full Industrial Temperature Range
•Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options –8-lead SOIC (150-mil Wide)
–8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)
1.Description
The AT25F512B is a rial interface Flash memory device designed for u in a wide variety of high-volume consumer bad applications in which program code is shad-owed from Flash memory into embedded or external RAM for execution. The flexible era architecture of the AT25F512B, with its era granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices.
The era block sizes of the AT25F512B have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the era blocks, the memory space can be ud much more efficiently. Becau certain code modules and data storage gments must reside
by themlves in their own era regions, the wasted and unud memory space that occurs with large ctored and large block era Flash memory devices can be greatly reduced. This incread memory space efficiency allows additional code routines and data storage gments to be added while still maintaining the same overall device density.
The device also contains a specialized OTP (One-Time Programmable) Security Reg-ister that can be ud for purpos such as unique device rialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for u in 3-volt systems, the AT25F512B supports read, pro-gram, and era operations with a supply voltage range of 2.7V to 3.6V. No parate
voltage is required for programming and erasing.
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AT25F512B [Preliminary]
2.Pin Descriptions and Pinouts
Table 2-1.
Pin Descriptions
Symbol
Name and Function
Asrted State
Type
CS CHIP SELECT: Asrting the CS pin lects the device. When the CS pin is deasrted, the device will be delected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance state. When the device is delected, data will not be ac
cepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally lf-timed operation such as a program or era cycle, the device will not enter the standby mode until the completion of the operation.
Low Input
SCK SERIAL CLOCK: This pin is ud to provide a clock to the device and is ud to control the flow of data to and from the device. Command, address, and input data prent on the SI pin is always latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.
-Input
SI SERIAL INPUT: The SI pin is ud to shift data into the device. The SI pin is ud for all data input including command and address quences. Data on the SI pin is always latched in on the rising edge of SCK.
Data prent on the SI pin will be ignored whenever the device is delected (CS is deasrted).
-Input
SO SERIAL OUTPUT: The SO pin is ud to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK.
The SO pin will be in a high-impedance state whenever the device is delected (CS is deasrted).
-Output
WP WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Plea refer to “Protection Commands and Features” on page 11 for more details on protection features and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be ud. However, it is recommended that the WP pin also be externally connected to V CC whenever possible.
Low Input
HOLD
HOLD: The HOLD pin is ud to temporarily pau rial communication without
delecting or retting the device. While the HOLD pin is asrted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asrted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition paus rial communication only and does not have an effect on internally lf-timed operations such as a program or era cycle. Plea refer to “Hold” on page 24 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be ud. However, it is recommended that the HOLD pin also be externally connected to V CC whenever possible.
Low Input
V CC
DEVICE POWER SUPPLY: The V CC pin is ud to supply the source voltage to the device.Operations at invalid V CC voltages may produce spurious results and should not be attempt
ed.
-Power
GND GROUND: The ground reference for the power supply. GND should be connected to the system ground.
-Power
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AT25F512B [Preliminary]
3.Block Diagram
Figure 3-1.
Block Diagram
Figure 2-1.最性感的美女
8-SOIC Top View
Figure 2-2.8-UDFN (Top View)
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AT25F512B [Preliminary]
4.Memory Array
To provide the greatest flexibility, the memory array of the AT25F512B can be erad in three levels of granularity including a full chip era. The size of the era blocks is optimized for both code and data storage applications, allowing both code and data gments to reside in their own era regions. The Memory Architecture Diagram illustrates the breakdown of each era level.Figure 4-1.
Memory Architecture Diagram
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AT25F512B [Preliminary]
5.Device Operation
The AT25F512B is controlled by a t of instructions that are nt from a host controller, com-monly referred to as the SPI Master. The SPI Master communicates with the AT25F512B via the SPI bus which is comprid of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and pha and how the polarity and pha control the flow of
data on the SPI bus. The AT25F512B supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data).With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK.Figure 5-1.
SPI Mode 0 and 3
6.Commands and Addressing
pin has been asrted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and data bytes are trans-Opcodes not supported by the AT25F512B will be ignored by the device and no operation will be started. The device will continue to ignore any data prented on the SI pin until the start of the next operation (CS pin being deasrted and then reasrted). In addition, if the CS pin is deas-rted before complete opcode and address information is nt to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation.
Addressing of the device requires a total of three bytes of information to be nt, reprenting address bits A23-A0. Since the upper address limit of the AT25F512B memory array is 00FFFFh, address bits A23-A16 are always ignored by the device.
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AT25F512B [Preliminary]
Table 6-1.
Command Listing
Command
Opcode
Clock Frequency
《离骚》Address Bytes
Dummy Bytes
Data Bytes
Read Commands
Read Array
0Bh 0000 1011Up to 70 MHz 311+03h
0000 0011
Up to 33 MHz
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软件测试优秀简历
1+
Program and Era Commands
情愿Block Era (4 Kbytes)20h 0010 0000Up to 70 MHz 300Block Era (32 Kbytes)
52h 0101 0010Up to 70 MHz 300D8h 1101 1000Up to 70 MHz 300Chip Era
60h 0110 0000Up to 70 MHz 000C7h 1100 0111Up to 70 MHz 000Chip Era (Legacy Command)62h 0110 0010Up to 70 MHz 000Byte/Page Program (1 to 256 Bytes)02h
0000 0010
Up to 70 MHz
3
1+
Protection Commands
Write Enable 06h 0000 0110Up to 70 MHz 000Write Disable 04h
0000 0100
Up to 70 MHz
Security Commands
Program OTP Security Register 9Bh 1001 1011Up to 70 MHz 301+Read OTP Security Register 77h
0111 0111
Up to 70 MHz
3
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1+
Status Register Commands
Read Status Register 05h 0000 0101Up to 70 MHz 001+Write Status Register 01h
0000 0001
Up to 70 MHz
1
Miscellaneous Commands
Read Manufacturer and Device ID 9Fh 1001 1111Up to 70 MHz 00 1 to 4Read ID (Legacy Command)15h 0001 0101Up to 70 MHz 002Deep Power-Down
B9h 1011 1001Up to 70 MHz 000Resume from Deep Power-Down
ABh
1010 1011
Up to 70 MHz
