General Description
The MAX6340/MAX6421–MAX6426 low-power micro-processor supervisor circuits monitor system voltages from 1.6V to 5V. The devices perform a single function:they asrt a ret signal whenever the V CC supply volt-age falls below its ret threshold. The ret output remains asrted for the ret timeout period after V CC ris above the ret threshold. The ret timeout is exter-nally t by a capacitor to provide more flexibility.
The MAX6421/MAX6424 have an active-low, push-pull ret output. The MAX6422 has an active-high,push-pull ret output and the MAX6340/MAX6423/MAX6425/MAX6426 have an active-low, open-drain ret output. The MAX6421/MAX6422/MAX6423 are offered in 4-pin SC70 or SOT143 packages. The MAX6340/MAX6424/MAX6425/MAX6426 are available in 5-pin SOT23-5 packages.
Applications
Portable Equipment
Battery-Powered Computers/Controllers Automotive Medical Equipment Intelligent Instruments Embedded Controllers Critical µP Monitoring Set-Top Boxes Computers
Features
o Monitor System Voltages from 1.6V to 5V o Capacitor-Adjustable Ret Timeout Period o Low Quiescent Current (1.6µA typ)o Three RESET Output Options
Push-Pull RESET Push-Pull RESET Open-Drain RESET o Guaranteed Ret Valid to V CC = 1V o Immune to Short V CC Transients
o Small 4-Pin SC70, 4-Pin SOT143, and 5-Pin SOT23Packages o MAX6340 Pin Compatible with LP3470o MAX6424/MAX6425 Pin Compatible with NCP300–NCP303, MC33464/MC33465,S807/S808/S809, and RN5VD o MAX6426 Pin Compatible with PST92XX
MAX6340/MAX6421–MAX6426
Low-Power, SC70/SOT µP Ret Circuits with Capacitor-Adjustable Ret Timeout Delay
________________________________________________________________Maxim Integrated Products
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Ordering Information
Pin Configurations
19-2440; Rev 2; 10/02
For pricing, delivery, and ordering information,plea contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at
Typical Operating Circuit appears at end of data sheet.Selector Guide appears at end of data sheet.
Note: The MAX6340/MAX6421–MAX6426 are available with fac-tory-trimmed ret thresholds from 1.575V to 5.0V in approxi-mately 0.1V increments. Inrt the desired nominal ret threshold suffix (from Table 1) into the blanks. There are 50 stan-dard versions with a required order increment of 2500 pieces.Sample stock is generally held on standard versions only (e Standard Versions Table). Required order increment is 10,000pieces for nonstandard versions. Contact factory for availability.All devices are available in tape-and-reel only.
M A X 6340/M A X 6421–M A X 6426
Low-Power, SC70/SOT µP Ret Circuits with Capacitor-Adjustable Ret Timeout Delay
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
Stress beyond tho listed under “Absolute Maximum Ratings” may cau permanent damage to the device. The are stress ratings only, and functional operation of the device at the or any other conditions beyond tho indicated in the operational ctions of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All Voltages Referenced to GND
V CC ........................................................................-0.3V to +6.0V SRT, RESET , RESET (push-pull).................-0.3V to (V CC + 0.3V)RESET (open drain)...............................................-0.3V to +6.0V Input Current (all pins)......................................................±20mA Output Current (RESET , RESET)......................................±20mA
Continuous Power Dissipation (T A = +70°C)
4-Pin SC70 (derate 3.1mW/°C above +70°C)..............245mW 4-Pin SOT143 (derate 4mW/°C above +70°C).............320mW 5-Pin SOT23 (derate 7.1mW/°C above +70°C)............571mW Operating Temperature Range .........................-40°C to +125°C Storage -65°C to +150°C +150°C Lead Temperature (soldering, 10s)...................
..............+300°C
MAX6340/MAX6421–MAX6426
Low-Power, SC70/SOT µP Ret Circuits with Capacitor-Adjustable Ret Timeout Delay
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SUPPLY CURRENT vs. SUPPLY VOLTAGE
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SUPPLY VOLTAGE (V)
S U P P L Y C U R R E N T (µA )
0.11
100
10
1000
10,0000.001
0.1
0.01
110
100
1000
RESET TIMEOUT PERIOD vs. C SRT
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C SRT (nF)
R E S E T T I M E O U T P E R I O D
(m s )
4.10
4.20
4.15
4.25
4.30
-50
-25
25小免子
50
75
100
125
RESET TIMEOUT PERIOD vs. TEMPERATURE
TEMPERATURE (°C)
R E S E T T I M E O U T P E R I O D (m s )
RESET TIMEOUT PERIOD vs. TEMPERATURE
200
250350300500550450400600R E S E T T I M E O U T P E R I O D (µs )-50
25
-25
50
75
100125
TEMPERATURE (°C)0
50
25100751501251750
400
200
600
800
1000
MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE
RESET THRESHOLD OVERDRIVE (mV)
T R A N S I E N T D U R A T I O N (µs )
V CC
TO RESET DELAY
vs. TEMPERATURE (V CC FALLING)
8090
110100140150130120160
V C C T O R E S E T D E L A Y (µs )-50
25
-25
50
75100
125
TEMPERATURE (°C)
按需印刷
POWER-UP/POWER-DOWN
CHARACTERISTIC
1V/div
1V/div
400µs/div
0.994
0.9980.9961.0021.0001.0041.006-502550-25075100125
NORMALIZED RESET THRESHOLD
vs. TEMPERATURE
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TEMPERATURE (°C)
N O R M A L I Z E D R E S E T T H R E S H O L D
Typical Operating Characteristics
(V CC = 5V, C SRT = 1500pF, T A = +25°C, unless otherwi noted.)
M A X 6340/M A X 6421–M A X 6426
Low-Power, SC70/SOT µP Ret Circuits with Capacitor-Adjustable Ret Timeout Delay
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Detailed Description
Ret Output
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The ret output is typically connected to the ret input of a µP. A µP ’s ret input starts or restarts the µP in a known state. The MAX6340/MAX6421–MAX6426 µP supervisory circuits provide the ret logic to prevent code-execution errors during power-up, power-down,and brownout conditions (e Typical Operating Characteristics ).
RESET changes from high to low whenever V CC drops below the threshold voltage. Once V CC exceeds the threshold voltage, RESET remains low for the capacitor-adjustable ret timeout period.
The MAX6422 active-high RESET output is the inver logic of the active-low RESET output. All device outputs are guaranteed valid for V CC > 1V.
The MAX6340/MAX6423/MAX6425/MAX6426 are open-drain RESET outputs. Connect an external pullup resis-tor to any supply from 0 to 5.5V. Select a resistor value large enough to register a logic low when RESET is asrted and small enough to register a logic high while supplying all input current and leakage paths connected to the RESET line. A 10k Ωto 100k Ωpullup is sufficient in most applications.
Selecting a Ret Capacitor
The ret timeout period is adjustable to accommodate a variety of µP applications. Adjust the ret timeout period (t RP ) by connecting a capacitor (C SRT ) between SRT and ground. Calculate the ret timeout capacitor as follows:
RESET Output Allows U with Multiple Supplies
MAX6340/MAX6421–MAX6426
Low-Power, SC70/SOT µP Ret Circuits with Capacitor-Adjustable Ret Timeout Delay
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C SRT = (t RP - 275µs) / (2.73 ✕106)
where t RP is in conds and C SRT is in farads.
The ret delay time is t by a current/capacitor-con-trolled ramp compared to an internal 0.65V reference.An internal 240nA ramp current source charges the external capacitor. The charge to the capacitor is cleared when a ret condition is detected. Once the ret condition is removed, the voltage on the capacitor ramps according to the formula: dV/dt = I/C. The C SRT capacitor must ramp to 0.65V to deasrt the ret.C SRT must be a low-leakage (<10nA) type capacitor;ceramic is recommended.
Operating as a Voltage Detector
The MAX6340/MAX6421–MAX6426 can be operated in a voltage detector mode by floating the SRT pin. The ret delay times for V CC rising above or falling below the threshold are not significantly different. The ret output is deasrted smoothly without fal puls.
Applications Information
Interfacing to Other Voltages for Logic
Compatibility
The open-drain outputs of the MAX6340/MAX6423/MAX6425/MAX6426 can be ud to interface to µPs with other logic levels. As shown in Figure 1, the open-drain output can be connected to voltages from 0 to 5.5V. This allows for easy logic compatibility to various µPs.
Wired-OR Ret
To allow auxiliary circuitry to hold the system in ret,an external open-drain logic signal can be connected to the open-drain RESET of the MAX6340/MAX6423/MAX6425/MAX6426, as shown in Figure 2. This config-uration can ret the µP, but does not provide the ret timeout when the external logic signal is relead.Negative-Going V CC Transients
In addition to issuing a ret to the µP during power-up,power-down, and brownout conditions, the supervisors are relatively immune to short-duration negative-going transients (glitches). The graph Maximum Transient Duration vs. Ret Threshold Overdrive in the Typical Operating Characteristics shows this relationship.
The area below the curve of the graph is the region in which the devices typically do not generate a ret pul. This graph was generated using a negative-going pul applied to V CC , starting above the actual ret threshold (V TH ) and ending below it by the magni-tude indicated (ret-thre
shold overdrive). As the mag-nitude of the transient decreas (farther below the ret threshold), the maximum allowable pul width decreas. Typically, a V CC transient that goes 100mV below the ret threshold and lasts 50µs or less does not cau a ret pul to be issued.
Ensuring a Valid RESET or RESET
Down to V CC = 0
When V CC falls below 1V, RESET /RESET current-sink-ing (sourcing) capabilities decline drastically. In the ca of the MAX6421/MAX6424, high-impedance CMOS-logic inputs connected to RESET can drift to undetermined voltages. This prents no problems in most applications, since most µPs and other circuitry do not operate with V CC below 1V.
In tho applications where RESET must be valid down to zero, adding a pulldown resistor between RESET and ground sinks any stray leakage currents, holding RESET low (Figure 3). The value of the pulldown resis-tor is not critical; 100k Ωis large enough not to load RESET and small enough to pull RESET to ground. For applications using the MAX6422, a 100k Ωpullup resis-
M A X 6340/M A X 6421–M A X 6426
Low-Power, SC70/SOT µP Ret Circuits with Capacitor-Adjustable Ret Timeout Delay
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tor between RESET and V CC holds RESET high when V CC falls below 1V (F igure 4). Open-drain RESET ver-sions are not recommended for applications requiring valid logic for V CC down to zero.
Layout Consideration
SRT is a preci current source. When developing the layout for the application, be careful to minimize board capacitance and leakage currents around this pin.Traces connected to SRT should be kept as short as possible. Traces carrying high-speed digital signals and traces with large voltage potentials should be rout-ed as far from SRT as possible. Leakage current and stray capacitance (e.g., a scope probe) at this pin could cau errors in the ret timeout period. When evaluating the parts, u clean prototype boards to ensure accurate ret periods.
Figure 3. Ensuring RESET Valid to V CC
= 0
CC
