1
Standard Products
UT28F256 Radiation-Hardened 32K x 8 PROM
Data Sheet
December 2002
FEATURES
q Programmable, read-only, asynchronous, radiation-hardened, 32K x 8 memory
-Supported by industry standard programmer q 45ns and 40ns maximum address access time (-55 o C to +125 o C)
q TTL compatible input and TTL/CMOS compatible output levels q Three-state data bus
q Low operating and standby current
-Operating: 125mA maximum @25MHz •Derating: 3mA/MHz
-Standby: 2mA maximum (post-rad)q Radiation-hardened process and design; total do irradiation testing to MIL-STD-883, Method 1019-Total do: 1E6 rad(Si)
- LET TH (0.25) ~ 100 MeV-cm 2/mg
- SEL Immune >128 MeV-cm 2/mg
- Saturated Cross Section cm 2 per bit, 1.0E-11欣赏英语怎么说
- 1.2E-8 errors/device-day, Adams 90% geosynchronous
heavy ion
-Memory cell LET threshold: >128 MeV-cm 2/mg
q QML Q & V compliant part -AC and DC testing at factory1995年农历
q Packaging options:
-28-lead 50-mil center flatpack (0.490 x 0.74)
-28-lead 100-mil center DIP (0.600 x 1.4) - contact factory q V DD : 5.0 volts + 10%
q Standard Microcircuit Drawing 5962-96891
PRODUCT DESCRIPTION
The UT28F256 amorphous silicon anti-fu PROM is a high performance, asynchronous, radiation-hardened,
32K x 8 programmable memory device. The UT28F256 PROM features fully asychronous operation requiring no external clocks or timing strobes. An advanced radiation-hardened twin-well CMOS process technology is ud to implement the UT28F256. The combination of radiation-hardness, fast access time, and low power consumption make the UT28F256 ideal for high speed systems designed for operation in radiation environments.
DECODER
MEMORY ARRAY
SENSE AMPLIFIER
PROGRAMMING
CONTROL LOGIC
DQ(7:0)
A(14:0)CE PE OE
Figure 1. PROM Block Diagram
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DEVICE OPERATION
The UT28F256 has three control inputs: Chip Enable (CE), Program Enable (PE), and Output Enable (OE); fifteen address inputs, A(14:0); and eight bidirectional data lines, DQ(7:0). C E is the device enable input that controls chip lection, active, and standby modes. Asrting C E caus I
DD to ri to its active value and decodes the fifteen address inputs to lect one of 32,768 words in the memory. PE controls program and read operations. During a read cycle, OE must be asrted to enable the outputs.PIN NAMES
Table 1. Device Operation Truth Table 1
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
ABSOLUTE MAXIMUM RATINGS 1(Referenced to V SS )
Notes:
1.Stress outside the listed absolute maximum ratings may cau permanent damage to the device. This is a stress rating only, and functional operation of the device at the or any other conditions beyond limits indicated in the operational ctions of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.Test per MIL-STD-883, Method 1012, infinite heat sink.
A14A12A7A6A5A4A3A2A1A0DQ0DQ1DQ2V SS
V DD PE A13A8A9A11OE A10CE DQ7DQ6DQ5DQ4DQ3
PIN CONFIGURATION
1234567891011121314
2827262524232221201918171615
A(14:0)Address CE Chip Enable OE Output Enable PE Program Enable DQ(7:0)
Data Input/Data Output
OE PE CE I/O MODE MODE X 11Three-state Standby 010Data Out Read 100Data In Program 1
1
Three-state
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Read 2
SYMBOL PARAMETER
LIMITS UNITS V DD DC supply voltage -0.3 to 7.0V V I/O Voltage on any pin -0.5 to (V DD + 0.5)V T STG Storage temperature -65 to +150
°C P D Maximum power dissipation 1.5W T J Maximum junction temperature +175°C ΘJC Thermal resistance, junction-to-ca 2 3.3
°C/W I I
DC input current
±10
mA
3
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*(V DD = 5.0V ±10%; -55°C < T C < +125°C)Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rad(Si).
1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one cond.
4. Functional test.
5. Derates at 3.0mA/MHz.
SYMBOL PARAMETER
LIMITS UNITS V DD Positive supply voltage 4.5 to 5.5V T C Ca temperature range -55 to +125°C V IN
DC input voltage
0 to V DD
V
SYMBOL PARAMETER CONDITION
MINIMUM
MAXIMUM
UNIT V IH High-level input voltage (TTL) 2.4
V V IL Low-level input voltage (TTL)
0.8V V OL1Low-level output voltage I OL = 4.0mA, V DD = 4.5V (TTL)0.4V V OL2Low-level output voltage I OL = 200µA, V DD = 4.5V (CMOS)V SS + 0.10V V OH1High-level output voltage I OH = -200µA, V DD = 4.5V (CMOS)V DD -0.1V V OH2High-level output voltage I OH = -2.0mA, V DD = 4.5V (TTL) 2.4
V C IN 1Input capacitance
ƒ = 1MHz, V DD = 5.0V V IN = 0V
15
pF
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C IO 1, 4Bidirectional I/O capacitance ƒ = 1MHz, V D
D = 5.0V V OUT = 0V
15pF
I IN Input leakage current V IN = 0V to V DD -55µA I OZ
Three-state output leakage current
V O = 0V to V DD V DD = 5.5V OE = 5.5V
-10
10
µA
I OS 2,3Short-circuit output current V DD = 5.5V, V O = V DD V DD = 5.5V, V O = 0V
-9090
mA mA
I DD1(OP)5
Supply current operating @25.0MHz (40ns product)@22.2MHz (45ns product)TTL inputs levels (I OUT = 0), V IL = 0.2V
V DD , PE = 5.5V
125117mA mA I DD2(SB)post-rad
Supply current standby
CMOS input levels V IL = V SS +0.25V CE = V DD - 0.25 V IH = V DD - 0.25V
嫩茶
2
mA
4
READ CYCLE
A combination of PE greater than V IH (min), and CE less than V IL (max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output.
An address access read is initiated by a change in address inputs while the chip is enabled with O E asrted and PE deasrted. Valid data appears on data output, DQ(7:0), after the specified t AVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time.
The chip enable-controlled access is initiated by C E going active while OE remains asrted, PE remains deasrted, and the address remain stable for the entire cycle. After the specified t ELQV is satisfied, the eight-bit word addresd by A(14:0) appears at the data outputs DQ(7:0).
Output enable-controlled access is initiated by OE going active while CE is asrted, PE is deasrted, and the address are stable. Read access time is t GLQV unless t AVQV or t ELQV have not been satisfied.
AC CHARACTERISTICS READ CYCLE (Post-Radiation)*(V DD = 5.0V ±10%; -55°C < T C < +125°C)
Notes:
惺忪* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rads(Si).1. Functional test.
2. Three-state is defined as a 400mV change from steady-state output voltage.
SYMBOL PARAMETER 28F256-45 MIN MAX 28F256-40 MIN MAX UNIT t AVAV 1Read cycle time 45
40
ns t AVQV Read access time 45
40
ns t AXQX 2Output hold time
00ns t GLQX 2OE-controlled output enable time 0
ns t GLQV OE-controlled access time 1515ns t GHQZ OE-controlled output three-state time 15
15
ns t ELQX 2 CE-controlled output enable time 0
ns t ELQV CE-controlled access time 4540ns t EHQZ
CE-controlled output three-state time
15
15
ns
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RADIATION HARDNESS
The UT28F256 PROM incorporates special design and layout features which allow operation in high-level radiation
environments. UTMC has developed special low-temperature processing techniques designed to enhance the total-do
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radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup immunity, UTMC builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. In addition, UTMC pays special attention to power and ground distribution during the design pha, minimizing do-rate upt caud by rail collap.
RADIATION HARDNESS DESIGN SPECIFICATIONS 1Note:
1.The PROM will not latchup during radiation exposure under recommended operating conditions.
Figure 2. PROM Read Cycle
沙坑跳远A(14:0)CE
OE
Total Do
1E6rad(Si)Latchup LET Threshold >128MeV-cm 2/mg Memory Cell LET Threshold >128MeV-cm 2/mg Transient Upt LET Threshold
54MeV-cm 2/mg
Transient Upt Device Cross Section @ LET=128 MeV-cm 2/mg
1E-6
cm 2