Chapter 2:Configuration Interfaces
7.On some Xilinx PROMs, the ret polarity is programmable. Ret should be
configured as active Low when using this tup.
动物简笔8.The Xilinx PROM must be t for parallel mode. This mode is not available for all
devices.
9.When configuring a Virtex-5 device in SelectMAP mode from a Xilinx configuration
PROM, the RDWR_B and CS_B signals can be tied Low (e “SelectMAP Data
Loading”).
10.The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page73.
11.Ganged SelectMap configuration is specific to the Platform Flash XCFS and XCFP
PROM only.
If one device is designated as the Master, the DONE pins of all devices must be connected
with the active DONE drivers disabled. An external pull-up resistor is required on the
common DONE signal. Designers must carefully focus on signal integrity due to the
恩施有什么好玩的
incread fanout of the outputs from the PROM. Signal integrity simulation is
recommended.
Readback is not possible if the CS_B signals are tied together, becau all devices
simultaneously attempt to drive the D signals.
SelectMAP Data Loading
红星照耀中国读后感500字The SelectMAP interface allows for either continuous or non-continuous data loading.
Data loading is controlled by the CS_B, RDWR_B, CCLK, and BUSY signals.
CS_B
The Chip Select input (CS_B) enables the SelectMAP bus. When CS_B is High, the Virtex-5
device ignores the SelectMAP interface, neither registering any inputs nor driving any
outputs. D and BUSY are placed in a High-Z state, and RDWR_B is ignored.
∙If CS_B = 0, the device's SelectMAP interface is enabled.
∙If CS_B = 1, the device's SelectMAP interface is disabled.
For a multiple device SelectMAP configuration, refer to Figure2-12.
If only one device is being configure through the SelectMAP and readback is not required,
or if ganged SelectMAP configuration is ud, the CS_B signal can be tied to ground, as
illustrated in Figure2-9 and Figure2-13.
RDWR_B
RDWR_B is an input to the Virtex-5 device that controls whether the data pins are inputs or
outputs:
∙If RDWR_B = 0, the data pins are inputs (writing to the FPGA).
∙If RDWR_B = 1, the data pins are outputs (reading from the FPGA).
For configuration, RDWR_B must be t for write control (RDWR_B=0). For readback,
RDWR_B must be t for read control (RDWR_B=1) while CS_B is deasrted. (For
details, refer to Chapter7, “Readback and Configuration Verification.”)
Changing the value of RDWR_B while CS_B is asrted triggers an ABORT if the device
gets a rising CCLK edge (e “SelectMAP ABORT”). If readback is not needed, RDWR_B
can be tied to ground or ud for debugging with SelectMAP ABORT.
SelectMAP Configuration Interface The RDWR_B signal is ignored while CS_B is deasrted. Read/write control of the
3-stating of the data pins is asynchronous. The FPGA actively drives SelectMAP data
without regard to CCLK if RDWR_B is t for read control (RDWR_B=1, Readback) while CS_B is asrted.
CCLK
All activity on the SelectMAP data bus is synchronous to CCLK. When RDWR_B is t for write control (RDWR_B=0, Configuration), the FPGA samples the SelectMAP data pins on rising CCLK edges. When RDWR_B is t for read control (RDWR_B=1, Readback), the FPGA updates the SelectMAP data pins on rising CCLK edges.
In Slave SelectMAP mode, configuration can be paud by stopping CCLK (e “Non-新木偶奇遇记
Continuous SelectMAP Data Loading”).穆塔西姆
BUSY
BUSY is an output from the FPGA indicating when the device is ready to drive readback data. Unlike earlier Virtex devices, Virtex-5 FPGAs never drive the BUSY signal High
during configuration, even at the maximum configuration frequency with an encrypted bitstream. The Virtex-5 device only drives BUSY High during readback. (For details, refer to Chapter7, “Readback and Configuration Verification.”)
∙If BUSY = 0 during readback, the SelectMAP data pins are driving valid readback data.
∙If BUSY = 1 during readback, the SelectMAP data pins are not driving valid readback data.
When CS_B is deasrted (CS_B=1), the BUSY pin is placed in a High-Z state.
BUSY remains in a High-Z state until CS_B is asrted. If CS_B is asrted before power-up (that is, if the pin is tied to ground), BUSY initially is in a High-Z state, then driven Low after POR finishes, usually a few milliconds (T BUSY), after V CCINT reaches V POR but before INIT_B goes High.
Unless readback is ud, the BUSY pin can be left unconnected.
Continuous SelectMAP Data Loading
Continuous data loading is ud in applications where the configuration controller can provide an uninterrupted stream of configuration data. After power-up, the configuration controller ts the RDW
R_B signal for write control (RDWR_B=0) and asrts the CS_B signal (CS_B=0), causing the device to drive BUSY Low (this transition is asynchronous).
RDWR_B must be driven Low before CS_B is asrted, otherwi an ABORT occurs (e “SelectMAP ABORT”).
On the next rising CCLK edge, the device begins sampling the data pins. Only D[0:7] are sampled by Configuration until the bus width is determined. See “Bus Width Auto
Detection” for details. After bus width is determined, the proper width of the data bus is sampled for the Synchronization word arch. Configuration begins after the
synchronization word is clocked into the device.
After the configuration bitstream is loaded, the device enters the startup quence. The device asrts its DONE signal High in the pha of the startup quence that is specified by the bitstream (e “Startup (Step 8)” in Chapter1). The configuration controller should continue nding CCLK puls until after the startup quence has finished. (This can
Chapter 2:Configuration Interfaces
JTAG Configuration/Readback
2.Go to Shift-DR and load the following bitstream fragment to write the RCFG
command to the CMD register:
1111 1111 1111 1111 1111 1111 1111 1111 // Dummy word
1010 1010 1001 1001 0101 0101 0110 0110 // SYNCHWORD
0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP
0011 0000 0000 0000 1000 0000 0000 0001 // Write 1 word to CMD reg
0000 0000 0000 0000 0000 0000 0000 0100 // RCFG command
0011 0000 0000 0000 0010 0000 0000 0001 // Write 1 word to FAR
0000 0000 0000 0000 0000 0000 0000 0000 // Frame address: Top row 0/CLB
// Block Type/Column 0/Frame 0 0010 1000 0000 0000 0110 0000 0000 0000 // Type 1 header: Read FDRO
0100 1bbb bbbb bbbb bbbb bbbb bbbb bbbb // Type 2 header: Readback
// wordcount (27 bits) - CLB
// frames only
0000 0000 0000 0000 0000 0000 0000 0000 // Flush pipeline
3.Load the CFG_OUT instruction into the JTAG IR.
4.Go to Shift-DR and shift out the readback data.吃什么最有营养
5.Go to Test-Logic-Ret (TLR).
Readback - Type 2: Including Block RAM Frames
1.Load the CFG_IN instruction into the JTAG IR.
2.Go to Shift-DR and load the following bitstream fragment to clear the CRC_ERROR
signal:
笔力
1111 1111 1111 1111 1111 1111 1111 1111 // Dummy word
1010 1010 1001 1001 0101 0101 0110 0110 // SYNCHWORD
0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP
0011 0000 0000 0000 1000 0000 0000 0001 // Write 1 word to CMD reg
0000 0000 0000 0000 0000 0000 0000 0111 // RCRC command
0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP
0000 0000 0000 0000 0000 0000 0000 0000 // flush pipeline
3.Load the JSHUTDWN instruction into the JTAG IR.
4.Go to Run-Test-Idle (RTI).
5.Clock TCK for 12 cycles to clock the shutdown quence (asrts GTS_CFG and
deasrts GWE and DONE).
6.Load the CFG_IN instruction into the JTAG IR.
7.Go to Shift-DR and load the following bitstream fragment to write the RCFG
command to the CMD register:
1111 1111 1111 1111 1111 1111 1111 1111 // Dummy word
1010 1010 1001 1001 0101 0101 0110 0110 // SYNCHWORD
0010 0000 0000 0000 0000 0000 0000 0000 // NO-OP
0011 0000 0000 0000 1000 0000 0000 0001 // Write 1 word to CMD reg
0000 0000 0000 0000 0000 0000 0000 0100 // RCFG command
0011 0000 0000 0000 0010 0000 0000 0001 // Write 1 word to FAR
0000 0000 0000 0000 0000 0000 0000 0000 // Frame address: Top row 0/CLB
// Block Type/Column 0/Frame 0 0010 1000 0000 0000 0110 0000 0000 0000 // Type 1 header: Read FDRO
荷兰足球0100 1bbb bbbb bbbb bbbb bbbb bbbb bbbb // Type 2 header: Readback
// wordcount (27 bits) - CLB
// and Block RAM frames
0000 0000 0000 0000 0000 0000 0000 0000 // Flush pipeline
8.Load the CFG_OUT instruction into the JTAG IR.
Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1
