4.5 PHY Update
The DFI contains signals to support a MC-initiated and a PHY-initiated update process.
The signals ud in the update interface are: dfi_ctrlupd_req, dfi_ctrlupd_ack,
2014年新年贺词dfi_phyupd_req, dfi_phyupd_type and dfi_phyupd_ack. For more information on
the signals, refer to Section 3.4, “Update Interface”.
4.5.1 MC-Initiated Update
During normal operation, the MC may encounter idle time during which no commands
are being issued to the memory devices and all outstanding read and write data have
have been transferred on the DFI. Asrtion of the dfi_ctrlupd_req signal indicates the
control, read and write interfaces on the DFI are idle. While the dfi_ctrlupd_ack signal
is asrted, the DFI bus may only be ud for commands related to the update process.
The MC guarantees that dfi_ctrlupd_req signal will be asrted for at least tctrlupd_min
cycles, allowing the PHY time to respond. The PHY may respond or ignore the update
request. To acknowledge the request, the dfi_ctrlupd_ack signal must be asrted while
the dfi_ctrlupd_req signal is asrted. The dfi_ctrlupd_ack signal must de-asrt at
least one cycle before tctrlupd_max expires.
The MC must hold the dfi_ctrlupd_req signal as long as the dfi_ctrlupd_ack signal is
asrted, and must de-asrt the dfi_ctrlupd_req signal before tctrlupd_max expires.
Note that the number of cycles after the dfi_ctrlupd_ack signal de-asrts before the
dfi_ctrlupd_req signal de-asrts is not specified by the DFI. This situation is shown in
重操旧业的意思Figure 20.
It is important to note that the dfi_ctrlupd_ack signal is not required to asrt when the
dfi_ctrlupd_req signal is asrted. The MC must asrt the dfi_ctrlupd_req signal for
at least tctrlupd_min within every tctrlupd_interval
cycles, but the total number of cycles
that the dfi_ctrlupd_req signal is asrted must not exceed tctrlupd_max. This scenario
is shown in Figure 21.
4.5.2 PHY-Initiated Update教育改革心得体会
The PHY may also trigger the DFI into an idle state. This update process utilizes three
signals: dfi_phyupd_req, dfi_phyupd_type and dfi_phyupd_ack. The
dfi_phyupd_req signal indicates the need for idle time on the DFI, the
dfi_phyupd_type signal defines the type of update required, and the dfi_phyupd_ack
signal is the MC’s respon signal. Four update types are specified by the DFI.
To request an update, the dfi_phyupd_type signal must be valid when the
dfi_phyupd_req signal is asrted. The tphyupd_typeX parameters indicate the number
of cycles of idle time on the DFI control, read and write data interfaces being requested.
The dfi_phyupd_ack signal must asrt within tphyupd_resp cycles after the asrtion of
霸气歌曲the dfi_phyupd_req signal.
When the dfi_phyupd_ack signal is asrted, it must remain asrted until the
dfi_phyupd_req signal de-asrts or until tphyupd_typeX cycles have expired. The
dfi_phyupd_ack signal must de-asrt one cycle after the de-asrtion of the
dfi_phyupd_req signal. While the dfi_phyupd_ack signal is asrted, the DFI bus may
only be ud for commands related to the update process.
Unlike MC-initiated updates, the MC must respond to a PHY update request as shown
in Figure 22.
4.6 DFI Clock Disabling
青葱年少The DFI contains a dfi_dram_clk_disable signal which controls the DRAM clock
signal to the DRAM device(s). In the default state, the DRAM clock functions normally
and the dfi_dram_clk_disable bits are all de-asrted. If the system requires the clocks
雏形是什么意思
of the memory device(s) to be disabled, then the dfi_dram_clk_disable signal will be
asrted. For more information on the dfi_dram_clk_disable signal, refer to
Section 3.5, “Status Interface”.
Two timing parameters tdram_clk_disable and tdram_clk_enable indicate the number of DFI
cycles that the PHY requires to respond to the asrtion and de-asrtion of the
dfi_dram_clk_disable signal. The tdram_clk_disable value determines the number of
DFI cycles in which a rising edge of the dfi_dram_clk_disable signal affects the
DRAM clock and tdram_clk_enable ts the number of cycles required for the DRAM
clock to be active again, as shown in Figure 23.
一切如你4.7 Frequency Ratios Across the DFI
In a DDR memory subsystem, it may be advantageous to operate the PHY at a higher
frequency than the MC. If the PHY operates at a multiple of the MC frequency, the PHY
