Features
• Eight Pairs of Differential Clocks • Low skew < 50ps
• Low Cycle-to-cycle jitter < 50ps • Output Enable for all outputs • Outputs Tristate control via SMBus • Power Management Control • Programmable PLL Bandwidth • PLL or Fanout operation • 3.3V Operation
• Packaging (Pb-Free & Green):— 48-Pin SSOP (V) — 48-Pin TSSOP (A)
Description
PI6C20800 is a high-speed, low-noi differential clock buffer designed to be a companion to PI6C410B. The device distributes the differential SRC clock from PI6C410B to eight differential pairs of clock outputs either with or without PLL. The input SRC clock can be divided by 2 when SRC_DIV# is LOW. The clock outputs are controlled by input lection of SRC_STOP#, PWRDWN# and SMBus,
SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated. When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.
PCI Express Chipts
Pin Configuration
V DD_A V SS_A I REF LOCK OE_7OE_4OUT7OUT7#OE_INV V DD OUT6OUT6#OE_6OE_5OUT5OUT5#V SS V DD OUT4OUT4#PLL_BW#SRC_STOP PWRDWN# V SS
484746454443424140393837363534333231302928272625
123456789101112131415161718192021222324
SRC_DIV#
V DD V SS SRC SRC#OE_0OE_3OUT0OUT0#VSS V DD OUT1OUT1#OE_1OE_2OUT2OUT2#V SS V DD OUT3OUT3#
一年级数学日记PLL/BYPASS#
SCLK SDA
研究生找工作PI6C20800
1:8 Clock Driver for Intel
PCI Express Chipts
Pin Descriptions
Pin Name Type Pin #Descriptions
SRC_DIV#Input1 3.3V LVTTL input for lecting input frequency divide by 2,
active LOW.
SRC & SRC#Input4, 50.7V Differential SRC input from PI6C410 clock synthesizer
OE [0:7]Input6, 7, 14, 15, 35, 36,
43, 44 3.3V LVTTL input for enabling outputs, active HIGH.
OE_INV Input403.3V LVTTL input for inverting the OE, SRC_STOP# and PWRDWN# pins.
When 0 = same stage
When 1 = OE[0:7], SRC_STOP#, PWRDWN# inverted.
OUT[0:7] & OUT[0:7]#Output
8, 9, 12, 13, 16 17,
20, 21, 29, 30, 33, 34,
玻恩
37, 38, 41, 42
0.7V Differential outputs
PLL/BYPASS#Input22 3.3V LVTTL input for lecting fan-out of PLL operation. SCLK Input23SMBus compatible SCLOCK input
SDA I/O24SMBus compatible SDATA
最佳辩手
I REF Input46External resistor connection to t the differential output current SRC_STOP#Input27 3.3V LVTTL input for SRC stop, active LOW
PLL_BW#Input28 3.3V LVTTL input for lecting the PLL bandwidth PWRDWN# Input26 3.3V LVTTL input for Power Down operation, active LOW LOCK Output45 3.3V LVTTL output, transition high when PLL lock is achieved
(Latched output)
V DD Power2, 11, 19, 31, 39 3.3V Power Supply for Outputs
V SS Ground3, 10, 18, 25, 32Ground for Outputs羊肚怎么做好吃又简单
V SS_A Ground47Ground for PLL
V DD_A Power48 3.3V Power Supply for PLL
Serial Data Interface (SMBus)
PI6C20800 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below.
Address assignment
A6A5A4A3A2A1A0R/W 11011100/1 Data Protocol(1)
1 bit7 bits118 bits18 bits18 bits18 bits1 1 bit
Start bit Slave
Addr R/W Ack
Register
offt Ack
Byte
Count
= N
Ack Data
Byte 0Ack
Data
Byte N
- 1
Ack Stop
bit
Note:
1. Register offt for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
PI6C20800
1:8 Clock Driver for Intel
PCI Express Chipts
Data Byte 0: Control Register
Bit Descriptions
Type Power Up Condition
Output(s) Affected Pin 0
SRC_DIV#0 = Divide by 21 = Normal RW
1 = x1
OUT[0:7], OUT[0:7]#
NA
1PLL/BYPASS#0 = Fanout 1 = PLL
RW 1 = PLL OUT[0:7], OUT[0:7]#NA
2PLL Bandwidth
0 = HIGH Bandwidth,1 = LOW Bandwidth RW 1 = Low OUT[0:7], OUT[0:7]#NA 3TBD NA 4TBD NA 5TBD
NA
6
SRC_STOP#
0 = Driven when stopped 1 = Tristate
泰迪多少钱一只RW
0 = Driven when stopped
OUT[0:7], OUT[0:7]#
7PWRDWN#
鼻窦炎怎么办0 = Driven when stopped 1 = Tristate
RW 0 = Driven when stopped OUT[0:7], OUT[0:7]#NA
Data Byte 1: Control Register
Bit Descriptions
Type Power Up Condition
Output(s) Affected Pin 0OUTPUTS enable 1 = Enabled 0 = Disabled RW 1 = Enabled OUT0, OUT0#NA 1RW 1 = Enabled OUT1, OUT1#NA 2RW 1 = Enabled OUT2, OUT2#NA 3RW 1 = Enabled OUT3, OUT3#NA 4RW 1 = Enabled OUT4, OUT4#NA 5RW 1 = Enabled OUT5, OUT5#NA 6RW 1 = Enabled OUT6, OUT6#NA 7
RW
1 = Enabled
OUT7, OUT7#
NA
PI6C20800
1:8 Clock Driver for Intel
PCI Express Chipts
Data Byte 2: Control Register
Bit Descriptions
郑伊健版
Type Power Up Condition Output(s) Affected Pin 0Allow control of OUTPUTS with asrtion of SRC_STOP#0 = Free running
1 = Stopped with SRC_Stop#
RW 0 = Free running OUT0, OUT0#NA 1RW 0 = Free running OUT1, OUT1#NA 2RW 0 = Free running OUT2, OUT2#NA 3RW 0 = Free running OUT3, OUT3#NA 4RW 0 = Free running OUT4, OUT4#NA 5RW 0 = Free running OUT5, OUT5#NA 6RW 0 = Free running OUT6, OUT6#NA 7
RW
0 = Free running
OUT7, OUT7#
NA
Data Byte 3: Control Register
Bit Descriptions
Type Power Up Condition
Output(s) Affected
Pin
0TBD RW 1RW 2RW 3RW 4RW 5RW 6RW 7
RW
Data Byte 4: Pericom ID Register
Bit Descriptions
Type Power Up Condition
Output(s) Affected
Pin 0Pericom ID R 0NA NA 1R 0NA NA 2R 0NA NA 3R 0NA NA 4R 0NA NA 5R 1NA NA 6R 0NA NA 7
R
NA
NA
PI6C20800
1:8 Clock Driver for Intel
PCI Express Chipts
Functionality
PWRDWN#
OUT OUT#SRC_Stop#
OUT OUT#1Normal Normal 1Normal Normal 0
I REF × 2 or Float
LOW
I REF × 6 or Float
LOW
Figure 1. Power down quence
