1:20 Differential Clock/Data Fanout Buffer
FastEdge™ Series
CY2DP3120
Features
•Twenty ECL/PECL differential outputs
•One ECL/PECL compatible differential or single-ended clock inputs
•One HSTL compatible differential or single-ended clock inputs
•Hot-swappable/-inrtable •50 ps output-to-output skew •150 ps device-to-device skew •500 ps propagation delay (typical)•1.4 ps RMS period jitter (max.)
•1.5 GHz Operation (2.7 GHz max. toggle frequency)•PECL mode supply range: V CC = 2.5V± 5% to 3.3V±5% with V EE = 0V
•ECL mode supply range: V E E = –2.5V± 5% to –3.3V±5% with V CC = 0V
•Industrial temperature range: –40°C to 85°C •52-pin 1.4-mm TQFP package
•Temperature compensation like 100K ECL •Pin compatible with MC100ES6221
Functional Description
The CY2DP3120 is a low-skew, low propagation delay 1-to-20differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz.The device features two differential input paths that are multi-plexed internally. This mux is controlled by the CLK_SEL pin.The CY2DP3120 may function not only as a differential clock buffer but also as a signal-level translator and fanout on ECL/PECL signal to twenty ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpo. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypasd to ground via a 0.01-µF capacitor. Traditionally, in ECL, it is ud to provide the reference level to a receiving single-ended input that might have a different lf-bias point.
Since the CY2DP3120 introduces negligible jitter to the timing budget, it is the ideal choice for distrib
uting high frequency,high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation,ensure that the CY2DP3120 delivers consistent performance over various platforms.
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Governing Agencies
The following agencies provide specifications that apply to the CY2DP3120. The agency name and relevant specification is listed below in Table 2. Pin Definitions [1, 2, 3]
Pin
Name
I/O
诸暨旅游景点大全
Type
Description
3CLK_SEL I,PD ECL/PECL/HSTL Input clock lect 4CLKA, I,PD ECL/PECL Differential input clocks 6VBB [3]O
Bias Reference voltage output 5CLKA#I,PD/PU ECL/PECL Differential input clocks
7CLKB, I,PD
HSTL Alternate differential input clocks 8CLKB#I,PD/PU HSTL Alternate differential input clocks 9
VEE [2]-PWR Power Negative supply 1,2,14,27,40
VCC思悼电影
+PWR Power Positive Supply 52,50,48,46,44,42,39,37,35,33,31,29,26,24,22,20,18,16,13,11
Q(0:19)O
ECL/PECL
True output
51,49,47,45,43,41,38,36,34,32,30,28,25,23,21,19,17,15,12,10Q#(0:19)O ECL/PECL Complement output
Table 1.
Control Operation
CLK_SEL
0CLKA, CLKA# input pair is active (Default condition with no connection to pin)
CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations 1
CLKB, CLKB# input pair is active.
CLKB can be driven with HSTL-compatible signals with respective power configurations
Table 2.
Agency Name Specification
JEDEC
JESD 020B (MSL)JESD 51 (Theta JA)JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
Mil-Spec
883E Method 1012.1 (Thermal Theta JC)
Notes:
1.In the I/O column, the following notation is ud: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2.In ECL mode (negative power supply mode), V EE is either –
3.3V or –2.5V and V CC is connected to GND (0V). In PECL mode (positive power supply mode), V EE is connected to GND (0V) and V CC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V CC ) and are between V CC and V EE .
3.V BB is available for u for single-ended bias mode for |3.3V| supplies (not |2.5V|).
Absolute Maximum Ratings
Parameter Description Condition Min.Max.Unit V CC Positive Supply Voltage Non-Functional–0.3 4.6V V EE Negative Supply Voltage Non-Functional-4.60.3V T S Temperature, Storage Non-Functional–65+150°C T J Temperature, Junction Non-Functional150°C ESD h ESD Protection Human Body Model2000V M SL Moisture Sensitivity Level3N.A. Gate Count Total Number of Ud Gates Asmbled Die50gates Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply quencing is NOT required.
Operating Conditions
Parameter Description Condition Min.Max.Unit I BB Output Reference Current Relative to V BB|200|uA LU I Latch Up Immunity Functional, typical100mA T A Temperature, Operating Ambient Functional–40+85°C ØJc Dissipation, Junction to Ca Functional22[4]°C/W ØJa Dissipation, Junction to Ambient Functional60[4]°C/W I EE Maximum Quiescent Supply Current V EE pin250[5]mA C IN Input pin capacitance3pF L IN Pin Inductance1nH V IN Input Voltage Relative to V CC[6]–0.3V CC + 0.3V V TT Output Termination Voltage Relative to V CC[6]V CC – 2V V OUT Output Voltage Relative to V CC[6]–0.3V CC + 0.3V I IN Input Current (ECL,PECL and HSTL)[7]V IN = V IL, or V IN = V IH l150l uA
PECL/HSTL DC Electrical Specifications
Parameter Description Condition Min.Max.Unit
V CC Operating Voltage 2.5V ± 5%, V EE = 0.0V
3.3V ± 5%, V EE = 0.0V 2.375
3.135
2.625
3.465
V
V
V CMR PECL Input Differential Crosspoint
Voltage[8]
Differential operation 1.2V CC V
V X HSTL Input Differential Crosspoint Volt-
age[9]Standard Load Differential
Operation
0.680.9V
V OH Output High Voltage I OH = –30 mA[10]V CC – 1.25V CC – 0.7V
V OL Output Low Voltage
V CC = 3.3V ± 5%
V CC = 2.5V ± 5%I OL = –5 mA[10]
V CC – 1.995
V CC –1.995
V CC – 1.5
V CC – 1.3
V
V
V IH Input Voltage, High Single-ended operation V CC – 1.165V CC – 0.880 [11]V
V IL Input Voltage, Low Single-ended operation V CC – 1.945 [11]V CC – 1.625V
V BB[3]Output Reference Voltage Relative to V CC[6]V CC – 1.620V CC – 1.220V Notes:
4.Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1
5.Power Calculation: V CC * I EE +0.5 (I OH + I OL) (V OH – V OL) (number of differential outputs ud); I EE does not include current going off chip.
6.where V CC is 3.3V±5% or 2.5V±5%
7.Inputs have internal pull-up/pull-down or biasing resistors which affect the input current.
8.Refer to Figure 1
9.V X(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the V X(AC) range and the input
swing lies within the V DIF(AC) specification. Violation of V X(AC) or V DIF(AC) impacts the device propagation delay, device and part-to-part skew. Refer to Fig. 2.
10.Equivalent to a termination of 50Ωto VTT. I OHMIN=(V OHMIN-V TT)/50; I OHMAX=(V OHMAX-V TT)/50; I OLMIN=(V OLMIN-V TT)/50; I OLMAX=(V OLMAX-V TT)/50;
11.V IL will operate down to V EE; V IH will operate up to V CC
ECL DC Electrical Specifications
Parameter Description Condition Min.Max.Unit
V EE Negative Power Supply–2.5V ± 5%, V CC = 0.0V
–3.3V ± 5%, V CC = 0.0V –2.625
–3.465
–2.375
–3.135
V
V CMR ECL Input Differential cross point
voltage[8]
炒冷面的做法
Differential operation V EE + 1.20V V V OH Output High Voltage I OH = –30 mA[10]–1.25–0.7V
V OL Output Low Voltage
V EE = –3.3V ± 5%
V EE = –2.5V ± 5%I OL = –5 mA[10]
–1.995
–1.995
–1.5
–1.3
V
V IH Input Voltage, High Single-ended operation–1.165–0.880 [11]V建筑环境与设备工程
V IL Input Voltage, Low Single-ended operation–1.945 [11]–1.625V
V BB[3]Output Reference Voltage– 1.620 – 1.220V
AC Electrical Specifications
Parameter Description Condition Min.Max.Unit V PP ECL/PECL Differential Input Voltage[8]Differential operation0.1 1.3 V
F CLK Input Frequency50% duty cycle Standard load 1.5GHz T PD Propagation Delay CLKA or CLKB to
Output pair
660 MHz [13]400750ps
V DIF HSTL Differential Input Voltage[12]Duty Cycle Standard Load
Differential Operation行政部长
0.4 1.9V
Vo Output Voltage (peak-to-peak; e
Figure3)
< 1 GHz0.375–V
V CMRO Output Common Voltage Range威斯敏斯特宫
(typical)
V CC – 1.425V tsk(0)Output-to-output Skew660 MHz [13], See Figure 3–50ps tsk(PP)Part-to-Part Output Skew660 MHz [13]–150ps
T PER Output Period Jitter (rms)[14]660 MHz [13]– 1.4ps tsk(P)Output Pul Skew[]660 MHz [13], See Figure 3–50ps
语文真好T R,T F Output Ri/Fall Time (e Figure3)660 MHz 50% duty cycle
Differential 20% to 80%笑傲红尘
0.080.3ns
Notes:
12.V DIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew
13.50% duty cycle; standard load; differential operation
14.For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pul Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000
data points
Output pul skew is the absolute difference of the propagation delay times: | t PLH – t PHL |.
Timing Definitions
Figure 2. HSTL Differential Input Waveform Definitions
for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
