专利名称：Twisted-ring oscillator and delay line
generating multiple phas using
白菜炒鸡蛋
differential dividers and comparators to
match delays
发明人：Christopher G. Arcus
申请号：US09683040
申请日：20011112
黑八规则
公开号：US06426662B1
快语公开日：
cad画椭圆>疫情班会
文章简历
short反义词
社交电视20020730
专利内容由知识产权出版社提供
专利附图：
摘要：A pha-locked loop (PLL) or a delay-locked loop (DLL) has differential delay
stages with differential outputs driving differential clock inputs to a pair of differential toggle flip-flops. One flip-flop changes state on the rising edge and the other on the falling edge of the true output from the delay stage. Differential-to-single-ended buffers convert differential flip-flop outputs to single-ended multi-pha clocks. To avoid erratic or multiple oscillation and overtones, fewer than eight and preferably four differential delay stages are ud. The delay stages are arranged in a twisted-ring with the differential outputs of the last delay stage crosd over and fed back to the differential inputs of the first delay stage. Tail currents of the delay stages can be adjusted by a voltage generated by a PLL loop. The differential toggle flip-flops allow for many taps or clock phas to be generated from the few delay stages.
申请人：PERICOM SEMICONDUCTOR CORP.
代理人：Stuart T. Auvinen
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