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ANTC206
Differential Clock Translation
Introduction
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Considering that each available clock logic type (LVPECL, HCSL, CML, and LVDS) operates with a different common-mode voltage and swing level than the next (e Table 1), it is necessary to design clock logic translation between the driver side and receiver side for any given system design. This application note details how to translate one differential clock into other types of differential logics by adding attenuation resistors and bias circuits between them to attenuate the swing level and re-bias the common-mode for the input of the receiver. Table 1. Common-Mode Voltage and Swing Levels of Different Clock Logic Types
Specification LVPECL LVDS CML Terminated 50Ω to V CC HCSL
V CM V CC− 1.4V 1.2V V CC− 0.2V 350mV
V SWING_SE800mV 325mV 400mV 700mV
V OH V CC− 1V 1.3625V V CC700mV
三国演义11V OL V CC− 1.8V 1.0375V V CC− 0.400V 0V Reference V CC Ground V CC Ground
燕分飞Input/Output Structure of Each Differential Clock Logic
Prior to designing the logic translation circuit, an examination of the input/output structures of each logic type −LVPECL, HCSL, CML, and LVDS − is required as each logic type features a different common-mode voltage and swing level.
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Low-Voltage, Positive-Referenced, Emitter-Coupled Logic (LVPECL)
Low-voltage, positive-referenced, emitter-coupled logic (LVPECL) originates from emitter-coupled logic (ECL), adopting a positive power supply.
The LVPECL input is a current-switching differential pair with high input impedance (e Figure 1). The input common-mode voltage should be approximately V CC− 1.3V for the purpo of having operating headroom, either from internal lf-biasing or external biasing.
The LVPECL output consists of a differential pair amplifier which drives a pair of emitter followers (or open emitters) as illustrated in Figure 1. The output emitter followers should operate in the “active” region with DC current at all times. The output pins of OUT+ and OUT− are typically connected to differential transmission lines (Z0 = 100Ω) or a single-ended transmission line (Z0 = 50Ω) for impedance matching. The proper termination for LVPECL output is 50Ω to V CC− 2V and OUT+/OUT− will typically be V CC− 1.3V, resulting in an approximate DC current flow of 14mA.
Another way to terminate LVPECL output is to apply 142Ωto GND, which provides a DC-biasing for LVPECL output and a DC current path to GND. Becau the LVPECL output common-mode is at V CC−1.3V, the DC-biasing resistor can be lected by assuming a DC current of 14mA (R = V CC− 1.3V / 14mA), resulting in R = 142Ω (150Ω also works) for V CC− 3.3V.
Figure 1. LVPECL Input/Output Structure
Low-Voltage Differential Signaling (LVDS)
Low-voltage differential signaling (LVDS) input requires a 100Ω termination resistor across the pins of IN+ and IN− with a common-mode voltage of approximately 1.2V (e Figure 2). If the 100Ω termination is not included on-chip, it must be included on the printed circuit board (PCB).
The LVDS output driver consists of a 3.5mA current source which is connected to differential outputs through a switching network. The output pins of OUT+ and OUT− are typically connecting to differential transmission lines (Z0 = 100Ω) or a single-ended transmission line (Z0 = 50Ω) for impedance matching − which are terminated with a 100Ω resistor across the receiver inputs − resulting in 350mV swing for LVDS logic (Figure 2).
Figure 2. LVDS Input/Output Structure
Current-Mode Logic (CML)
Most current-mode logic (CML) input structures have a 50Ω resistor to V CC on-chip (e Figure 3). If not, then one must be applied to VDD on both inputs of IN+ and IN− on the PCB. The input transistors are emitter followers which drive a differential-pair amplifier.
The CML output consists of a differential pair of common-emitter transistors with 50Ω collector resistors as the CML output structure illustrated in Figure 3 shows. The outputs of OUT+ and OUT− are typically connecting to differential transmission lines (Z0 = 100Ω) or a single-ended transmission line (Z0 = 50Ω) for impedance matching (Figure 3). The signal swing is provided by switching the current in a common-emitter differential BJT. Assuming the current source is 16mA (typical) and the CML output is loaded with a 50Ω resistor which is pull-up to VCC, this will result in an output voltage swing from V CC to V CC− 0.4V with a common-mode voltage (V CC− 0.2V).
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Figure 3. CML Input/Output Structure
High-Speed Current-Steering Logic
The high-speed current-steering logic (HCSL) input requires the single-ended swing of 700mV on both input pins of IN+ and IN− with a common-mode voltage of approximately 350mV (e Figure 4).
A typical HCSL driver is a differential logic with open-source outputs, where each of the output pins switches between 0 and 14mA. When one output pin is low (0), the other is high (driving 14mA). The output pins of OUT+ and OUT− are typically connecting to differential transmission lines (Z0 = 100Ω) or a single-ended transmission line (Z0 = 50Ω), which requires an external termination resistor (50Ω to GND), resulting in a 700mV swing level for HCSL input structures (Figure 4).
Figure 4. HCSL Input/Output Structure
LVPECL-to-CML Translation
狗怎么读As shown in Figure 5, placing a 150Ω resistor to GND at LVPECL driver output is esntial for the open emitter to provide the DC-biasing as well as a DC current path to GND. In order to attenuate the 800mV LVPECL swing to 400mV CML swing, place a 50Ω attenuating resistor (R A) after the 150Ω resistor to attenuate half of the LVPECL swing level. Additionally, lf-biasing inside the CML receiver input must be confirmed. If the lf-biasing at the input of CML is not prent, a 50Ω termination resistor to VCC must be placed on the PCB for CML biasing and transmission line termination.
Micrel’s ultra-low-jitter crystal oscillators and clock generators (i.e., MX55, MX57, SM802xxx, SM803xxx, MX85xxx) can provide <0.3ps RMS pha jitter with any type of output logics, except CML logic. With the below translation circuit, it is easy to achieve CML output from LVPECL logic.
Figure 5. LVPECL-to-CML Translation
