专利名称：Data packing in a 32-bit DMA architecture
发明人：Shashank Dabral,Ramanujan K Valmiki
建党101年申请号：US11483018
申请日：20060707
公开号：US07444442B2
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20081028泳镜防雾
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摘要：A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method compris the steps of identifying the optimal number of data elements, that can be accesd as a single full-word transfer,tting data packing criteria and analysing the data pattern and determining the impact
of offt direction on data packing. If the packing criteria are met, the data is compacted and fetched in four bytes or two half-words in one transaction by performing a full-word transfer instead of a partial transfer. If the packing criteria are not met, a single byte or a single half word is fetched. This invention provides a system for reducing data transfer overheads. The system compris of an external address generation unit for generating external memory address and corresponding byte enables and a read local address generation unit for generating internal memory address and corresponding byte enables.手绘墙
申请人：Shashank Dabral,Ramanujan K Valmiki
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地址：Flat No. 601, Kalyan Apartments, Sector-24, Indira Nagar Lucknow, Uttar Pradesh 226016 IN,Villa No. 23-1, Adarsh Palm Meadows, Airport Varthur-Whitefield Road, Ramagundahalli Bangalor丑星
e, Karnataka 560066 IN
国籍：IN,IN
代理人：Ash Tankha
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