安委会会议纪要
【例3-1】 2选1多路选择器程序。 （P31）
梵高星空LIBRARY IEEE; --IEEE库使用说明语句
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21 IS --实体说明部分
PORT(
a,b : IN STD_LOGIC;
s: IN STD_LOGIC;
y: OUT STD_LOGIC
);
END ENTITY mux21;
ARCHITECTURE mux21a OF mux21 IS --结构体说明部分
BEGIN
PROCESS(a,b,s)
BEGIN
IF s='0' THEN y<=a;
ELSE
y<=b;
END IF;
END PROCESS;
END ARCHITECTURE mux21a;
路由器如何设置【例3-2】 有类属说明的2输入与非门的实体描述。 （P33）
ENTITY nand2 IS
GENERIC ( t_ri : TIME := 2ns ;
t_fall : TIME := 1ns )
PORT( a: IN BIT;
防护层 b : IN BIT;
s : OUT BIT);
END ENTITY nand2;
【例3-3】 n输入与非门的实体描述： （P33）
ENTITY nand_n IS
GENERIC ( n : INTEGER ) ;
PORT( a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
s : OUT STD_LOGIC );
END ENTITY nand_n;
例3-4】 半加器的完整VHDL描述，其中x、y为加数与被加数，s为和信号，c为进位信号。 （P36）
ENTITY half_adder IS
PORT( x,y : IN BIT;
s: IN BIT;
c: OUT BIT);
END ENTITY half_adder;
ARCHITECTURE dataflow OF half_adder IS
BEGIN
s <= x XOR y;
c <= x AND y;
END ARCHITECTURE dataflow;
【例3-5】 2选1多路选择器的行为描述程序。 （P37）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21 IS
PORT(
a,b : IN STD_LOGIC;
s: IN STD_LOGIC;
y: OUT STD_LOGIC
);
END ENTITY mux21;
ARCHITECTURE behav OF mux21 IS
BEGIN
PROCESS(a,b,s)
BEGIN
IF s='0' THEN y<=a;
ELSE
y<=b;
END IF;
END PROCESS;
END ARCHITECTURE behav;
【例3-6】 2选1多路选择器数据流描述程序。 （P36）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21 IS
PORT(
a,b : IN STD_LOGIC;
s: IN STD_LOGIC;
y: OUT STD_LOGIC
);
END ENTITY mux21;
ARCHITECTURE dataflow OF mux21 IS
BEGIN
y<=(a AND (NOT s)) OR (b AND s);
END ARCHITECTURE dataflow;
【例3-7】 2选1多路选择器结构描述程序。 （P37）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY and21 IS
PORT(i0,i1 : IN STD_LOGIC;
q: OUT STD_LOGIC );
END ENTITY and21;
ARCHITECTURE one OF and21 IS
BEGIN
q<=i0 AND i1;
END ARCHITECTURE one;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or21 IS
PORT(i0,i1 : IN STD_LOGIC;
q: OUT STD_LOGIC );
END ENTITY or21;
ARCHITECTURE one OF or21 IS
BEGIN
q<=i0 OR i1;
END ARCHITECTURE one;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY inv21 IS
PORT(i0 : IN STD_LOGIC;
q: OUT STD_LOGIC );
END ENTITY inv21;
ARCHITECTURE one OF inv21 IS
BEGIN
q<= (NOT i0);
END ARCHITECTURE one;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21 IS
PORT(
a,b : IN STD_LOGIC;
s: IN STD_LOGIC;
y: OUT STD_LOGIC
);
END ENTITY mux21;
ARCHITECTURE struct OF mux21 IS
COMPONENT and21
PORT (i0,i1 : IN STD_LOGIC;
q: OUT STD_LOGIC);
END COMPONENT;
COMPONENT or21
PORT (i0,i1 : IN STD_LOGIC;
q: OUT STD_LOGIC);
END COMPONENT;
COMPONENT inv21
PORT (i0: IN STD_LOGIC;
q: OUT STD_LOGIC);
END COMPONENT;
SIGNAL tmp1,tmp2,tmp3:STD_LOGIC;
BEGIN
u1: and21 PORT MAP (b, s,tmp1);
u2: inv21 PORT MAP(s,tmp2);
u3: and21 PORT MAP (a,tmp2,tmp3);
u4: or21 PORT MAP(tmp1,tmp3,y);
END ARCHITECTURE struct;
【例3-8】 半加器的混合描述程序。 （P37）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY xor21 IS培新中学
PORT(i0,i1:IN STD_LOGIC;
q: OUT STD_LOGIC);
END ENTITY xor21;
ARCHITECTURE behav OF xor21 IS
BEGIN
q<=i0 XOR i1;
END ARCHITECTURE behav;因材施教
土豆咖喱饭的做法LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY half_adder IS
PORT(a,b:IN STD_LOGIC;
c,s: OUT STD_LOGIC);
END ENTITY half_adder;
ARCHITECTURE mix OF half_adder IS
COMPONENT xor21 IS
PORT(i0,i1:IN STD_LOGIC;
q:OUT STD_LOGIC);
END COMPONENT;
BEGIN
c <= a AND b;
u1: xor21 PORT MAP(a,b,s);
END ARCHITECTURE mix;
【例3-9】 打开一个字符文件，读出文件中的内容并关闭文件。 （P51）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY readfile IS
离职合同PORT( cs:IN STD_LOGIC;
c: OUT CHARACTER);
END ENTITY readfile;
ARCHITECTURE read1 OF readfile IS
