DATASHEET
Cadence PCB design solutions
are available in the following
p roduct suites:
• Cadence Allegro PCB Design L, XL, and GXL and options
• Cadence OrCAD PCB Designer,
Cadence OrCAD PCB Designer
with PSpice, and Cadence OrCAD
PCB Designer Basics
• Cadence OrCAD EE Designer and Cadence OrCAD EE Designer Plus Complex physical and electrical constraints, denly packed components, and faster high-speed technology requirements are just some of the things adding complexity to today’s PCB designs. Designers need the ability to easily
defi ne,
m anage, and validate simple physical/spacing constraints—as well as critical high-speed signals—at any stage of the design p rocess. At the same time, they must ensure that
the fi nal PCB meets performance, manufacturing, and test
s pecifi cations goals.
CADENCE PCB DESIGN: LAYOUT AND ROUTING
CADENCE PCB
DESIGN SOLUTIONS
Cadence® PCB design solutions are
c omplete design environments for
s olving and implementing the design
c hallenges an
d manufacturability
f2c视频c oncerns. The design s olutions contain
everything needed to take a PCB design
from concept to p roduction with a fully
integrated design fl ow including design
capture, c omponent tools, a PCB editor,
and an auto/interactive router as well
as i nterfaces for manufacturing, and
mechanical CAD. A common databa
architecture, u model and library offers
fully s calable PCB solutions for both
Cadence OrCAD® and Allegro® product
lines g iving you the a bility to grow and
expand as designs and design challenges
increa in complexity. The results are
incread p roductivity, shorter design
cycles, and faster ramp up to
volume production.
Cadence PCB design solutions are
a vailable in the following product suites:
• Cadence Allegro PCB Design L, XL,
and GXL and options
考研简历
• Cadence OrCAD PCB Designer,
Cadence OrCAD PCB Designer
with PSpice, and Cadence OrCAD
PCB Designer Basics
• Cadence OrCAD EE Designer and
Cadence OrCAD EE Designer Plus
BENEFITS
• Proven, scalable, cost-effective PCB
editing and routing solution that grows
as needed
• Provides a complete interconnect
e nvironment from basic/advanced
fl oorplanning and routing through
strategic planning and global routing
• Speeds advanced designs with
high-speed rules/constraints
• Includes a comprehensive feature t
• Features a front-to-back constraint management system for constraint creation, management, and validation
• Increas productivity through
a pplication integration
• Tight front-to-back integration FEATURES
PCB EDITOR TECHNOLOGY
PCB EDITING ENVIRONMENT
At the heart of Cadence PCB design
s olutions is a PCB editor—an i ntuitive, easy-to-u, constraint-driven
e nvironment for creating and editing simple to complex PCBs. Its extensive fea-ture t address a wide range o
f today’s design and m anufacturability challenges.
The PCB editor provides a powerful and fl exible t of fl oorplanning tools. PCB design partitioning technology, in the Allegro tiers, provides a concurrent design m ethodology for faster time to market and reduced layout time. Powerful shape-bad shove/hug interactive etch c reation/ editing provides a highly productive interconnect environment while providing real-time, heads-up displays of length and timing margins. Dynamic shape capability offers real-time copper pour plowing/ healing functionality during placement and routing iterations. The PCB editor can also generate a full suite of phototooling, bare-board fabrication and test outputs, including Gerber 274x, NC drill, and
bare-board test in a variety of formats. (See Figure 1.)
CONSTRAINT MANAGEMENT
A constraint management system d isplays physical/spacing and high-speed rules along with their status (bad on the
c urrent state of the design) in real time an
d is availabl
e at all stages o
f the design process. Each worksheet provides a
s preadsheet interface that enables the ur to defi ne, manage, and validate the different rules in a hierarchical fashion. This powerful application allows d esigners to graphically create, edit, and review
c onstraint ts as graphical topologies that act as electronic blueprints of an
ideal implementation strategy. Once the
constraints are prent in the databa,
they are ud to drive the placement and
routing p rocess for constrained s ignals.
The constraint management system is
c ompletely i ntegrate
d with th
e PCB e ditor
and c onstraints can be validated in real
time as the design process proceeds.
The results of the validation process is a
g raphical reprentation of constraint pass
or fail highlighted as green for passing
or red for failures. This allows designers
to immediately e the progress of the
design as well as the impact of any design
changes in the spreadsheets.
FLOORPLANNING
AND PLACEMENT
The constraint and rules-driven
m ethodology drives a powerful and
fl exible t of placement capabilities,
including interactive and automatic
component placement. The engineer
or designer can assign components
or s ubcircuits to specifi c “rooms”
d uring design entry or fl oorplanning.
Components can be fi ltered and lected
by reference designator, device p ackage/
footprint style, associated net name, part
number, or the schematic sheet/page
number. With thousands of c omponents
on today’s boards, needing preci
m anagement, real-time asmbly analysis
and feedback increas the designer’s
p roductivity and effi ciency by placing
components to corporate or EMS guide-
lines. Design-for-asmbly (DFA) analysis
(available in the Allegro PCB Design XL
and GXL tiers) offers this real-time pack-
age-to-package clearance checking during
300字的日记interactive component placement. Driven
from a two-dimensional spreadsheet
array of class and package instances,
real-time feedback provides minimum
c learance requirements ba
d on the
package’s side-to-side, side-to-end, or
end-to-end profi les. As a result, the PCB
designer can simultaneously place devices
for optimum routability, manufacturability,
and signal timing.
STRATEGIC PLANNING AND
DESIGN INTENT
Highly constrained, high-density designs
dominated by busd interconnect can
take signifi cant time to strategically
plan and route. Compound this with the
density issues of today’s components, new
signaling levels, and specifi c t opology
requirements, traditional CAD tools and
technologies fall short of being able
to capture a designer’s specifi c routing
intent and act upon it. The Global Route Figure 1: Cadence PCB design solutions bring together all the tools needed to design simple-to-complex PCBs
Environment technology (available only in Allegro PCB Design GXL) provides the technology and methodology to capture as well as adhere to a designer’s intent. Through the interconnect fl ow planning architecture and the global route engine, urs can for the fi rst time put their
e xperience and design intent into a tool that understands what they want—natively.
The solution accomplishes this by
a llowing the ur to create abstracted interconnect data (through the inter-connect fl ow p lanning architecture) and quickly converge on a solution and validate it with the global route engine. U of interconnect abstraction reduces the number of elements the system has to deal with. Reducing the number of e lements from potentially tens of
t housands of elements down to hundreds results in a signifi cant r eduction in the amount of manual interaction required. Additionally, it reduces the number of visual elements the ur es in the interconnect fl ow planning architecture, decreasing the number of elements they must physically manage. Using the abstract data, the planning and routing process can be accelerated by providing a visual/spatial map of the open area in relation to the abstract data and urs design intent. The route engine can then deal with the details of the r outing, adhering to the specifi ed intent, with-out the ur having to both visualize and solve the interconnect problems at the same time. This reprents a signifi -cant simplifi cation over current design tools allowing urs to get their designs c ompleted faster and more effi ciently. Urs can now converge on a successful interconnect solutio
n far faster and more easily than ever before, reducing design cycle time through incread effi ciency and productivity. (See Figure 2.)
DESIGN PARTITIONING
The increasing deployment of g lobally disperd design teams compounds the problems associated with trying to shorten design cycle times. Manual work-
arounds that address multi-ur
Figure 2: Interconnect fl ow planning allows urs to create abstracted interconnect data and quickly converge on a solution and validate it with the global route engine
challenges are time consuming, slow and prone to error. PCB design partitioning technology (available in the Allegro PCB design tiers) provides a multi-ur, concur-rent design methodology for faster time to market and reduction in layout time. Using this technology, multiple designers working concurrently on a layout share access to a single databa, regardless of team proximity. Design partitioning technology allows designers to partition designs into multiple ctions or areas for layout and editing by veral design team members. As a result, each designer can view all partitioned ct
ions and update the design view for monitoring the status and progress of other urs’ ctions. This can dramatically reduce overall design cycles and accelerate the design process.
INTERACTIVE ETCH EDITING
The interactive routing capability of the PCB editor provides powerful,
i nteractive features that deliver controlled
脚踝扭伤了怎么办a utomation to maintain ur control, while maximizing routing productiv-ity. Real-time, shape-bad, any angle, push/shove routing enables urs to choo between “shove-preferred,” “hug-preferred,” or “hug-only” modes. Shove-preferred mode allows urs to construct the optimum interconnect蓝牙耳机进水了还能用吗
path while the real-time, shape-bad router takes care of dynamically p ushing obstacles. Routes will automatically jump over obstacles such as pins or vias. The hug-preferred mode is the perfect solution when a d atabus needs to be constructed. In hug-preferred mode, the router contour follows other i nterconnect as a priority and only pushes aside or jumps obstacles when there is no other option. The hug-only option performs like the hug-preferred mode, but without the push-and-shove aggression on other etch objects. The real-time, embedded, shape-bad routing engine opti
mizes the route by either pushing obstacles or contour-following obstacles while dynamically jumping vias or component pins. During etch editing, the designer is
p rovided with a real-time, graphical heads-up display that shows how much timing slack remains for interconnect that has high-speed constraints. Interactive routing also provides the ability to
p erform group routing on multiple nets and interactive tuning of nets with high-speed length or delay constraints. (See Figure 3.)
DYNAMIC SHAPES
Dynamic shape technology offers real-time copper pour plowing/healing f unctionality. Shape parameters can be applied at three different l evels. Parameters are s tructured into global, shape instance, and object-level h ierarchies. Traces, vias, and
c omponents adde
d to a dynamic shap
e will a utomatically plow and void through the shape. When items are removed, the shape will auto
matically fi ll back in. Dynamic shapes do not require batch autovoiding or other post-processing steps after edits are made.
RF DESIGN
Design requirements involving high-performance/high-frequency circuits need to be solved faster and more accurately than ever before. The RF/mixed signal technology provides a complete, front-to-back solution from schematic to layout and manufacturing for PCB RF design. RF technology includes advanced RF capabilities, including intelligent layout functionality for parametrically creating and editing RF geometries and a fl exible shape editor. A bi-directional IFF interface provides quick and effi cient transfer of RF circuit data for simulation and valida-tion. This bi-directional fl ow eliminates the manual and error-prone iterations between circuit simulation and layout. (This feature is available in Allegro PCB Design XL and GXL-level tiers).
(See Figure 4.)
Figure 3: Dynamic push-and-shove capabilities make interactive editing easy on even the most advanced designs
PCB MANUFACTURING
A full suite of photo-tooling, bare-board fabrication and test outputs, including Gerber 274x, NC drill, and bare-board test in a variety of formats can be generated. More importantly, Cadence supports the industry initiative towards Gerber-less manufacturing through its Valor ODB++ interface that also includes the Valor Universal Viewer. The ODB++ data format creates accurate and reliable
m anufacturing data for high-quality, Gerber-less manufacturing.
PCB AUTOROUTER TECHNOLOGY
AUTOMATED INTERCONNECT ENVIRONMENT
Incread design complexity, density, and high-speed routing constraints make manual routing of PCBs diffi cult as well as time-consuming. The challenges of complex interconnect routing are solve
d with powerful, automated technology. This robust, production-proven a utorouter includes a batch r outing mode with e xtensive ur-defi ned r outing s trategy control as well as built-in automatic strategy capability. An interactive r outing environment—that features real-time interactive trace pushing and shoving—aids in m aking quick edits to traces. An interactive placement environment with extensive fl oorplanning f unctionality and complete component placement features eliminates the need to switch applications to make placement changes to optimize routing. By using the auto-interactive
fl oorplanning and placement capability, designers can improve routing quality and productivity, which are directly related to component placement. In addition, an extensive rule t allows designers to control a wide range of constraints from default board-level rules to rules by net/net class, and regions rules. High-speed routing features, available in the Allegro product tiers, provides c apabilities to h andle the net scheduling, timing,
c rosstalk, layer t routing, an
d special geometry requirements demanded by today’s high-speed circuits.
AUTOROUTNG
Advanced autorouting technol-ogy p rovides powerful, shape-bad a utorouting with fast, high c ompletion rates. Its routing algorithms are
designed to handle a wide range of PCB
i nterconnect challenges—from simple to complex, low density to high density—as well as the demands of high-speed constraints. The powerful algorithms make the most effi cient u of the r o uting area. To fi nd the best routing s olution for each ca, the router us a multi-pass, cost-bad, confl ict resolution
algorithms. An extensive rule t provides the c apability for physical and electrical constraint c ontrol. The extensive rule t has the fl exibility to handle specifi c rules on v arious routing elements in a design. Urs can defi ne rules required to meet common physical/spacing net rules and class rules to complex, hierarchical high-speed rules.
(See Figure 5.)
Figure 4: Complete front-to-back solution for
PCB RF design
Figure 5: Advanced autorouting technology effectively handles den, highly constrained designs
DESIGN FOR MANUFACTURING
The design for manufacturing c apability signifi cantly improves manufacturing yields. Manufacturing algorithms provide spreading capability that automatically increas conductor clearances on a space available basis. Automatic conductor spreading is ud to improve manufac-turability by repos
itioning conductors to create extra space between: conductors and pins, conductors and SMD pads, and adjacent conductor gments. Urs have the fl exibility to defi ne a range of s pacing values or to u the default v alues. Mitered corners and test points can be added throughout the routing process. The manufacturing algorithms auto-matically u the optimal tback range, starting from the largest to the smallest value. Test point inrtion a utomatically adds testable vias or pads as test points. Testable vias can be probed on the front, back, or both sides of the PCB, s upporting both single side and clamshell testers. Designers have the fl exibility to lect
the test point inrtion methodology
that conforms to their manufacturing
r equirements. Test points can be “fi xed” to avoid costly test fi xture modifi cations. Test point constraints include test probe surfaces, via sizes, via grids, and minimum center-to-center distance.
INTERACTIVE ROUTE EDITING
A route editor simplifi es and stream-
lines the etch editing process. As new
c onductors arerouted, the plowing f eature automatically pushes aside e xisting
c onductors an
d routes around pins. Using th
e shoving feature, d esigners can move conductor gments or vias against existing traces and push ahead over other pins and vias i
f necessary. A ghostin
g feature makes it easy to e valuate “what if” scenarios. As a conductor s egment
or via is moved under cursor control, the surrounding conductor is shoved and displayed dynamically so the adjusted routing can be evaluated before a ccepting a fi nal confi guration. The route editor is ideal for den, multilayer boards where legal via sites can be diffi cult to fi nd. Vias are positioned by simply clicking twice at a chon location. If possible, the
chon site is made available by shoving
c onductors aside on layers as needed. If
not, the route editor displays a design
rule violation and shows the legal via
sites nearby. In addition, the copyroute
f eature, which allows an existin
g route
to be copied to complete unrouted bus
c onnections, simplifi es bus construction.
PLACEMENT EDITING
The placement editor allows design-
ers to quickly place components while
simultaneously evaluating space, logic
乔任梁遗体
fl ow, and congestion before b eginning
the route or as needed during the r outing
process PCB. The Move mode allows
c omponents to be fl ipped, rotated,
aligned, pushed, and moved either as
individual components or as a group.
The Guided-Place mode lects the com-
ponent with the highest connectivity and
computes an optimal placement loca-
tion that does not violate design rules or
constraints. The location can be accepted
or rejected by the ur. Components
can be placed by directly entering
their X-Y l ocations. This capability is
p articularly uful for placing connectors
and c omponents with fi xed locations.
Density analysis graphically d isplays circuit
c ongestion by o verlaying the PCB with
a color map showing a range of areas—
from highly congested areas to lightly
congested. This helps determine where
placement a djustments could be made to
relieve c ongestion and improve routing
c ompletion. (See Figure 6.)
HIGH-SPEED CONSTRAINTS
High-speed routing constraints and
a lgorithms handle differential pairs,
net scheduling, timing, crosstalk, layer
t routing, and the special geometry
r equirements demanded by today’s high-
speed circuits. For differential pair r outing,
urs defi ne the gap between the two
conductors and the autorouter takes
care of the rest. The routing algorithms
intelligently handle routing around or
through vias, and automatically con-
forms to defi ned length or timing criteria.
Automatic net shielding is ud to reduce
Figure 6: Placement Editor allows you to evaluate
space, logic fl ow, and congestion at all stages of the
routing process
noi on noi-nsitive nets. Separate
design rules may be applied to differ-
ent regions of the design. For example,
urs can specify tight clearance rules in
the connector area of a design and less
s tringent rules elwhere.
PCB EDITOR INTEGRATION
The PCB routing technologies are
tightly integrated with the PCB edi-
tor. Through the PCB editor interface,
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all design i nformation and constraints
are a utomatically pasd to the router.
Once the route is completed, all route
i nformation is automatically pasd back
to the PCB editor.
DOCUMENTATION
Cadence tools provide an extensive
t of documentation, which includes
ur guides, context-nsitive help (F1),
r eference guides, online tutorial, and
multimedia demonstrations.
The documentation t helps you to:
• Find the answer you need by arching
the online help system and navigate
quickly between related topics with
extensive hypertext cross-references
• Learn the tool with the help of the
online interactive tutorial
• Find information on error and
warning scenarios
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