256Mb J-die SDRAM Specification
面膜的功效54 TSOP-II with Lead-Free & Halogen-Free
(RoHS compliant)
Industrial Temp. -40 to 85°C
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for u in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defen application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics rerves the right to change products or specification without notice.
Table of Contents
1.0 FEATURES (4)
2.0 GENERAL DESCRIPTION (4)
3.0 Ordering Information (4)
4.0 Package Physical Dimension (5)
人迹板桥霜
5.0 FUNCTIONAL BLOCK DIAGRAM (6)
6.0 PIN CONFIGURATION (7)
7.0 Input/Output Function Description (7)
8.0 ABSOLUTE MAXIMUM RATINGS (8)
9.0 DC OPERATING CONDITIONS (8)
10.0 CAPACITANCE (8)
11.0 DC CHARACTERISTICS (9)
12.0 AC OPERATING TEST CONDITIONS (10)
13.0 OPERATING AC PARAMETER (10)
14.0 AC CHARACTERISTICS (11)
15.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS (11)
16.0 IBIS SPECIFICATION (12)
17.0 SIMPLIFIED TRUTH TABLE (14)
Revision History
Revision Month Year History
1.0June2007 - First relea.
芹菜含钾高吗
1.1October2007 - Revid IDD current SPEC
- Revid typo of package dimension
- Added the comment of Halogen-free supporting
1.11March2008 - Added Package pin out lead width
Note 1 : 256Mb J-die SDR DRAMs support Lead-Free & Halogen-Free package with Lead-Free package code(-U).
Part No.
Orgainization Max Freq.Interface Package
K4S561632J-U *1I/P6016M x 16
会计专业毕业论文166MHz (CL=3)LVTTL
保加利亚深蹲
54pin TSOP(II)
Lead-Free & Halogen-Free *1
K4S561632J-UI/P75
133MHz (CL=3)
The K4S561632J is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16bits, fabri-cated with SAMSUNG's high performance CMOS technology. Synchronous design allows preci cycle control with the u of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be uful for a variety of high bandwidth, high performance memory system applications.
• JEDEC standard 3.3V power supply
痕迹是什么意思
• LVTTL compatible with multiplexed address • Four banks operation
• MRS cycle with address key programs -. CAS latency (2 & 3)
过程质量控制
-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • L(U)DQM (x16) for masking • Auto & lf refresh
• 64ms refresh period (8K Cycle)
• Lead-Free and Halogen-Free Package • RoHS compliant
• Support industrial Temp (-40 to 85 ’C)
4M x 16Bit x 4 Banks SDRAM Row & Column address configuration
Organization Row Address Column Address
16Mx16
A0~A12
A0-A8
1.0 FEATURES
2.0 GENERAL DESCRIPTION
3.0 Ordering Information
4.0 Package Physical Dimension洛阳纸贵的意思和典故
54Pin TSOP(II) Package Dimension
