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TSMC 0.25和0.35um 设计规则

更新时间:2023-05-16 16:37:18 阅读：评论：0

2 设计规则

2.1 设计规则几何关系定义

Width：

Sapcing:

Extension：一几何图形内边界到另一图形外边界长度

Overlap：一几何图形内边界到另一图形内边界长度

2.2 设计规则

[TSMC_0.35_4M2P_SUBM] lambda摇指倒装芯片＝0.2um

[TSMC_0.25_5M1P_DEEP] lambda＝0.12um

2.2.1 Well [1.1-1.4]

Rule	Description	SUBM 键盘布局	DEEP
1.1	Minimum width	12	四懂四会12
1.2	Minimum spacing between wells at different potential	18	18
1.3	Minimum spacing between wells at same potential	6	6
1.4	Minimum spacing between wells of different type	0	0

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Rule	Description	SUBM	DEEP
2.1	Minimum width	3	3
2.2	Minimum spacing	3 蝮蛇胶囊	3
2.3	Source/drain active to well edge	6	6
2.4	Substrate/well contact active to well edge	3	3
2.5	Minimum spacing between active of different implant	4	4

2.2.3 Thick Active [24.1-24.5]

THICK_ACTIVE is a layer ud for tho process offering two different thickness of gate oxide (typically for the layout of transistors that operate at two different voltage levels). The ACTIVE layer is ud to delineate all the active areas, regardless of gate oxide thickness. THICK_ACTIVE is ud to to mark tho ACTIV

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E areas that will have the thicker gate oxide; ACTIVE areas outside THICK_ACTIVE will have the thinner gate oxide.

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