AN1680/D
Design Considerations for Clamping Networks for Very High Voltage Monolithic Off-line PWM Controllers
Prepared by:Christophe BASSO
MOTOROLA SPS BP-1029, Le Mirail
31023 Toulou France
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email: R38010@m;Tel.: 33 5 61 19 90 12
INTRODUCTION
In the large family of Switch-Mode Power Supply (SMPS) components, the recently introduced high-voltage monolithic switchers start to play an important role. First of all becau they provide an easy mean to instantaneously build an efficient off-line supply but also becau their internal structure offers everything a designer needs:internal clock, pul-by-pul limitation, Leading Edge Blanking (LEB) etc. However, the internal MOSFET exhibits a low-energy capability body-diode which no longer protects the device against accidental avalanche.This element thus needs an adequate protection network against the electromagnetic leakage energy. This paper details what network is best adapted to the protection of
the devices and how to predict its efficiency in the application.
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The Leakage Inductance
Figure 1. shows a transformer wound across a standard magnetic material. The primary side made of Np turns creates the necessary force F which gives birth to two components: f m who links both windings, but also f l1which does not couple to the condary and corresponds to a leakage path through the air. Thanks to f m, a current Io circulates in the condary, but this current also gives birth to another leakage flux f l2 who polarity is opposite of that of f m. It is important to note that f m produces Io while f l2 is a conquence of it.
Figure 1. A Two-winding Transformer Showing the Leakage Paths
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As one can e from the picture, φl1 and φl2 clo through the air. As any (magnetic) medium, the air is affected by a Reluctance ℜ, or its inver, the permeance P.The permeances create in the primary and condary two leakage inductance with a value of: L leak = N 2 ⋅ P air , with N
being the primary or condary turns. As an effect, the parasitic leakage elements degrade the energy transfer between the primary and condary (ies). In a FLYBACK converter, the prence of the leakage element will a)generate a voltage spike at turn-off and b) divert a portion
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APPLICATION NOTE
of the primary current into the clamping network. Point a)implies the u of protection network to prevent a lethal drain voltage excursion while point b) explains the root of a degraded open-loop gain: the peak current needs to be higher than theoretically calculated to deliver the full rated output power.
The Principle of a Protection Network
The goal of the clamping network is to prevent the drain voltage to exceed a given limit. For instance, in the new ON Semiconductor MC3337X family, the maximum voltage shall stay within 700 V . A wor ca aris when the mains is at its highest level, e.g., 285 V AC in a universal mains application. To prevent the drain from reaching this value,Figure 2. (a) shows how a perfect network would work:when the MOSFET clos, the current builds-up in both
primary and leakage coils. When the ON periods stops, the MOSFET opens and interrupts its current. Since no current discontinuities can take place in an inductor, both magnetic fields collap and the voltage across the inductances revers in an attempt to keep the amps-turn constant: Lp energy is thus coupled to the condary and gives birth to the output current charge. Since L leakage cannot find a circulating path, it pulls-up 2 the drain voltage until D clamp starts to conduct and protects the switcher at a maximum theoretical level of: V mains + V clamp = 650 V . Figure 2. (b)shows the results of an INTUSOFT’s IsSpice4 (San Pedro,CA) simulations. When all the leakage energy is relead, a short parasitic oscillation takes place involving L leakage and all the parasitic capacitive elements prent in the circuit (transformer’s primary capacitance, MOSFET’s C oss etc.)
Figure 2. (a) A Simple FLYBACK Configuration Implementing a Clamping Network
V out
X2RATIO_POW = −0.183
Figure 2. (b) The Drain is Safely Clipped Below 700 V at High Mains
V D S
300100−100三门峡旅游
500700Diverting the Primary Current
Figure 2. (a) is interesting becau it helps understanding how the reflected condary voltage rets the leakage energy and how much of primary current this leakage inductance “steals away” by diverting it into the clamp.Everything is detailed on Figure 2. (c) graph. When the MOSFET turns-
off, a ret voltage is applied to the leakage inductance. This ret voltage depends on the clipping voltage but also on the FLYBACK’s. The higher this level,the faster the leakage energy drops to zero and authorizes the condary current to take place. The time Δt needed to complete the energy transfer is easily defined by:
D t +
L
leak @Ip V
clamp
*(V out )Vf c )@N ,where Ip is the final primary current, N the transformer ratio condary to primary, Vf c the condary diode forward drop and L leak the primary leakage inductance.Estimating the percentage of diverted current tells you the real peak current you will actually put in the primary to deliver the rated power. Figure 2. (c)’s Ipx point shows
where the condary diode catches-up with the primary
current. The slope of the decreasing primary current is simply
N @(V out )Vf c )
Lp
,
but this equation can also be written as:
Ip *Ipx D t +
N @(V out )Vf c )Lp
.Replacing Δt and solving for Ipx gives:
Ipx
Ip
+1*L
leak
Lp @
ǒ
V
clamp
(V out
)Vf)@N *1
Ǔ
This last equation gives you the effective percentage of primary current stolen by the leakage inductance. Applying Figure 2. numerical values gives: Ipx = 98.4% of Ip. Since Ip grows up to 2.73 A, then the theoretical peak condary current establishes at: 0.984 ⋅ 2.73 ⋅ 12.5 = 33.58 A.Figure 2. (d) validates the calculation.
Figure 2. (c) Waveforms at Turn-off: the Leakage Coil Prevents an Immediate Transfer
Figure 2. (d) IsSpice4 Simulation of Figure 2’s Circuit 10罗丛岩
20300
Protecting the MOSFET with an Active Element
The easiest way to clamp at a known level is to replace the null-impedance V clamp source by a zener diode or a transient suppressor. Figures 4. (a) and 4. (b) detail the connections and their associated waveforms. Since we have two diodes in ries, we have to care about both dissipated powers. Diodes can be modeled by a voltage source V (which equals V zener or V forward ) in ries with a dynamic resistance Rd. The total average conducted power dissipated is therefore:
P avg = V ⋅ I avg + R d ⋅ I 2rms.
For the zener diode, the first part is easily deducted from Figure 3. (b):
P avg 1+V z @Ip 2@
D t
T
or, once solving with Δt:
P avg 1+
V z @Ip 2
@L leak @F
2@(V z *(V out )Vf c )@N)
,
with F the switching frequency and V z the nominal zener level.
Figure 3. (a) Clipping with a Zener is Possible Solution
out
Figure 3. (b) Clipping Waveforms with a Zener Diode
V drain-source
V CC + V z
V O .N
To account for the Rd term, MOTOROLA specifies a clamping factor F C which gives the real peak zener voltage at a given peak current: V Z(Peak) = V Z(Nom) . F C . From this formula, we can write: V z(Nom) + Rd ⋅ I z(peak) = Fc ⋅V z(Nom). Solving for Rd gives:
Rd +
(Fc *1)@V
z(Nom)2
P
PK(Nom)
,
with P PK(Nom) being the maximum peak power accepted by
the zener diode or the transient suppressor. From Figure 3(b), let’s now calculate the RMS and average values of the zener current:
I zener (t)+Ip @D t *t D t
,
to obtain the RMS value simply solve:
1T
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D t
I 2zener(t).dt Ǹ or I zener RMS +Ip @
D t 3@T
Ǹ, T is the switching period. P avg 2 is thus:
P avg 2+
无花果味道Rd @Ip 2@F @D t 3
The I zener A VG value, which affects the conduction loss of the diode in ries with the zener is evaluated by:
I zener AVG +
Ip @D t @F 2
.
As we previously wrote, the diode conduction loss are expresd the same way as the zener’s, except that Rd +dVf
dId
extracted from the Vf versus Id curve in the diode data-sheet at Id = Ip. To summarize we have:
P
cond_zener +Ip 2@L
leak
@F @(V z )0.66@Rd @Ip)2@(V z *N @(V out )Vf c ))
P cond_diode +Ip 2@L leak @F @(V f
)0.66@Rd Ip @Ip)
2@(V z *N @(V out )Vf c ))
The final clipping level will be affected by two components: the zener clamping factor F C but also the time the ries diode takes to react. If we lect a fast MOTOROLA MUR160, the data-sheet specifies a turn-on time of 50 ns. In prence of drain voltage rising with a 1.5kV/μs slope, the diode will start to conduct at V mainsDC +Vz . F C . If we take the highest mains level of 275V AC and
a 180 V zener diode, then the ries diode starts to clip at 605 V . However, becau the injection time into the low-doped N-region takes about 50 ns, the dynamic resistance of the MUR160 gradually drops to its nominal value, accordingly generating an overshoot upon the drain.Measurements have to be carried upon the final board to confirm the safety of the final drain level.
Voltage at Turn-off MOSFET Clipping the Peak
RATIO_AUX = −0.156RATIO_AUX = −0.156
寿字书法图片大全When to U a Zener or a Transient Suppressor?
There are little technology differences behind a standard zener diode and a transient. However, the die area is far bigger for a transient suppressor than that of zener. A 5 W zener diode like the 1N5388B will accept 180 W peak power if it lasts less than 8.3 ms. If the peak current in the wor ca (e.g., when the PWM circuit maximum current limit works) multiplied by the nominal zener voltage exceeds the 180 W, then the diode will be destroyed when the supply experiences overloads. A transient suppressor like the P6KE200 still dissipates 5 W of continuous power but is able to accept surges up to 600 W @ 1 ms. If the peak power is really high, then turn to a 1.5KE200 which accepts up to 1.5 kW @ 1 ms.
A Passive RC Network to Clamp the Drain
If the above solution provides a stable clamping level rather independent from peak current variations, the cost of tho zener elements can degrade the overall price of your SMPS. The alternative lies in implementing a passive RC network as the one depicted in Figure 4. .
If we assume we do not have any external clipping network, we can calculate the amount of energy E T dissipated in the transistor every time it opens, assuming it would safely avalanche the voltage (Figure 4. (b)). As we said, the leakage tries to keep the current circulating at its level (Ip, when the transistor opens) during Δt and pushes the drain voltage up to BV DSS . Ip(t) can be expresd by:
Ip(t)+Ip @D t *t D t
.
