A Method to Model MOSFET’s Second Breakdown Action for Circuit-Level ESD Simulation
Qiang CUI 1,Yan HAN 1*,Juin J. LIOU 1,2,Shurong DONG 1, Ruijun SI1,and Cheng PENG1
1、Zhejiang university (Yuquan Campus) ,Hangzhou ,Zhejiang Province ,China,310027
2、College of Engineering and Computer Science in University of Central Florida,Florida of USA, 32816
* Email：hany@
Abstract
A method to exact the electrical parameters and model the “cond breakdown” action of MOSFET’s under ESD (Electro-Static Discharge) on circuit-level, using TCAD simulation, is prented. MOSFET is one of the most important ESD protection devices, and is widely ud as I/O protection device in integrated circuits. The avalanche breakdown of the MOSFET can be simulated by TCAD tools and the circuit-level model has been prented. However, accurate modeling and insightful analyzing of the “cond breakdown” action, which leads to the permanent failure of the MOSFET, is rarely reported. We prent an accurate macro model of the MOSFET bad on deep analyzing of the physical mecha
nism of the “cond breakdown”, using TCAD simulation. This macro model owns fine convergency and accuracy which are of importance to the simulation of the ESD protection ability of the ESD protection network on circuit and system level.
1. Introduction
MOSFET is one of the most important devices in ESD protection, and is widely ud as ESD protection device in I/O pads. As is shown in Fig. 1, the gate, source and substrate are connected to the ground, and the drain and I/O are connected to the same voltage. As is shown in Fig. 2, MOSFET ud as an ESD protection device is bad on its avalanche breakdown action. The leak current is quite small when the bias voltage of the gate-grounded NMOSFET (ggNMOS) is smaller than some value (Vt1); when the bias voltage exceeds Vt1, the ESD current will be relead becau of the avalanche breakdown, at the same time the voltage between the two ends of the device will be pulled back to some voltage (Vh), and therefore the ggNMOS is able to protect the I/O pads against the ESD overstress. If the current continue to ri to It2, the cond breakdown will occur in the MOSFET. Both the TCAD simulation of the avalanche breakdown and the circuit-level model has been prented. However, accurate modeling and insightful analyzing of the “cond breakdown” action, which leads to the permanent failure of the MOSFET, is rarely reported. A novel
method for modeling the MOSFET on circuit-level using TCAD tools is prented in this paper. 2. Review of Two Breakdowns
There are two breakdowns occur in MOSFETs if the ESD current is large enough under instantaneous ESD overstress. One is the “avalanche breakdown”, the other one is the “cond breakdown” (thermal breakdown). The carriers and lattice atoms within potential barrier region of the rever PN junction of the drain impact each other heavily under strong rever bias voltage and produce a first generation carriers, which will continue to impact the and generate a cond generation carriers and so on. Therefore the current will become larger and larger and finally the avalanche breakdown occurs.The “cond breakdown” is caud by the accumulated heat in the rever PN junction. The heat is produced by the large current going through the junction and cannot be dissipated rapidly enough. Then the temperature of the junction will ri until the device is burnt out. Generally the avalanche breakdown is recoverable and device will not be damaged, as long as the power pouring into the device is stopped in time. It is the “avalanche breakdown” of MOSFET that we usually utilize to protect the I/O pads against ESD overstress. On the other hand, the “cond breakdown” will make the device failure forever. So we have to leave the MOSFET enough area on the layout to avoid the “cond breakdown”. Bad on the physical mechanism of th
e first and the cond breakdowns, a novel macro model of the MOSFET is described in this paper.
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Fig.2 Typical I-V Characteristic
2.1 Avalanche Breakdown
The “avalanche breakdown” of the MOSFET can be modeled as the macro model as shown in Fig. 3. [1] The avalanche breakdown current Igen= (M-1)(Ic + Ids)；The multiplier of avalanche breakdown M = exp[ h1(vd - vd1)] + exp[ h2(vd-vd2)]；The substrate resistance Rsub = R1 + R2 + R3, where R1 is the drain resistance, R2 is the channel resistance and R3 is the source resistance; [2] The GP model is ud into the parasitic BJT; and Rd reprents the contact resistance. This macro model can describe the “avalanche breakdown” of the MOSFET. The “cond breakdown” action will be constructed bad on this macro model.
Fig.3 Macro Model of Avalanche Breakdown
2.2 Second Breakdown
Fig.4 Rectangular Box Heat Source Model (Zoom Out)
Fig.5 Rectangular Box Heat Source Model (Zoom In)
The heat source model shown in Fig. 4 and Fig. 5 is ud in the macro model to simulate the cond breakdown action. Both the electric criterion when the device enters the cond breakdown condition and the electric characteristic after the cond breakdown needs to be modeled in order to simulate the cond breakdown.
It is necessary to build a model which can accurately describe the mechanism of the cond breakdown of the MOSFET. The reason leading to the cond breakdown of the MOSFET is the heat accumulation effect caud by large eternal current pouring into drain and well. [3] [4] [5] The carriers will become more and more, as the high temperature in the drain and well has rin to 600-800K and therefore the resistance will decrea allowing more currents go through the device and increa the temperature of the device. If this positive feedback cannot be stopped rapidly, the current inside the device will accumulate in a small area instead of going through the junction uniformly. This large current with its hot effect will generate hot spot inside the device. The MOS transistor will be melt when the temperature of the hot spot ris to 1688K, and the junction between the drain and substrate will be shot. Rectangular source heat source can be introduced to model the electric criterion of the cond breakdown. [5] This modified model assumes all power accumulating in a cube with the horizontal length b between the drain and well area, the vertical length c and the depth a, as shown in Fig. 5. Take the definition of effective power is Peff=R(t)VI, where V is the voltage between two ends of the MOSFET, I is the current going through the device and R(t) is a coefficient. The periods in different ESD models differ from each other and correspondingly the R(t)s are different. The relation between incremental temperature of the hottest point inside the device ΔT(t) ( here the temperature of the hottest point is Tmax=T0+ΔT(t), with T0 initial temperature and T
max highest temperature of the device) and P eff is a gmental function shown in equations (1) to (4):
P eff=
反反
t
T
abcC
p
Δ
ρ (0≤t< t)
(1)
c
P eff=
2/
c
p
t
t
T
C
K
ab
−
Δ
ρ
π
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( t≤t< t
b
) (2)
c
P eff=
b
c
t
t
T
Ka
b
e
/
2
)
/
(
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4
−
+
Δ
π( t
b
≤t< t)
(3)
a
P eff=吃什么会变白
t
t
b
c
b
a
T
Ka
a
e
/
2/
2
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/
(
log
2
−
−
+
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π
(t≥ t)(4)
a In the equations, K is the thermal conductivity, C p is the heat capacity, D= K/ρC p, ρ is the densi
ty of the silicon, t= c
c
2/4πD, t= b
b
2/4πD , t= a
a
2/4πD,where K, C
p
, and ρ is dependent on the process, in this paper, we u HHNEC EE180G process where K=1.4Watt/cm⋅k, Cp=750J/kg⋅k, ρ=2.328E-3kg/cm3. We can calculate the highest temperature at every time point, and then calculate the concentration of the
heat-generating carriers N d caud by highest temperature. If N d extends the background dopant
concentration, the device will enter the condition of the “cond breakdown”, as is shown in equation (5). Put this equation into the thermal nsitive block and the cond breakdown action of MOSFET can be accurately described on circuit level.
N d =1.69×1019
exp(
max 10377.63
T ×−)⋅ 2/3)300
max (T (5)
The main work to model the electric characteristic of the cond breakdown is to model the thermal resistance under high temperature. After entering the condition of the cond breakdown, the positive feedback effect caud by hot spot could make the device temperature more than 1000K. We firstly t a specific temperature for the MOSFET using TCAD tools and get the resistance of the MOSFET at this temperature through device simulation. Then write this resistance rate into the block of the thermal resistance and therefore the resistance after the “cond breakdown” could be respec
tively accurately described on circuit level. 3. Schematic and Source Codes
Fig.6 Macro Model of Second Breakdown
As shown in Fig. 6, one MOSFET from the standard unit library (W=100μm, L=1.65μm), five parasitic blocks and one modulation resistor block are ud to simulate the breakdown characteristic of the fo
ur port MOSFET under instantaneous current overstress. The modulation resistor Rd is ud to reprent the contact resistor of the MOSFET. The avalanche current block IGEN, the avalanche resistance block RSUB, and the parasitic transistor block PBJT can describe the “avalanche breakdown” characteristic. The thermal nsitive block Switch and the thermal resistance block
Rthermal could simulate the “cond breakdown” characteristic. In the thermal nsitive block Switch, the
Verilog-A source codes to describe the criterion of the electro thermal uncontrollable condition are as follows:
Firstly, calculate the internal power of the MOSFET.
V(Sin,Path0)<+0;
Iinter=I(Sin,Path0);
Vsin=V(Sin,Vss); power=Vsin*Iinter;
Secondly, judge whether the internal power level will push the device into the electro thermal uncontr春风不改旧时波
ollable condition, which can be realized through detecting whether the hot carriers generated by heat at the inner hot spot exceed the background dopant concentration. Where Tc is the temperature of the inner hot spot of the MOSFET, Nd is the concentration of the carriers generated by the heat at the hot spot, and Nd0 is the background dopant concentration at the hot spot.
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Tc=Coe*power+T0; C=Tc/T0; D=pow(C,x); E=(-1)*B/Tc; Nd=A*D*exp(E);
If the device enters the electro thermal uncontrollable condition, the MOSFET will be switched into the thermal resistor mode.
if(Nd>=Nd0) begin
V(Sin,Path1)<+0; I(Sin,Path0)<+0; end el begin
V(Sin,Path0)<+0; I(Sin,Path1)<+0; End
Finally, the Verilog-A source codes to describe the resistor after thermal breakdown are as follows:
V(Ia,Ic)<+0;
V(Ra,Rc) <+ R0*I(Ra,Rc)+ V0;
Where Ia, Ic are the current input and output ports respectively, Ra, Rc are voltage ports, V0 is the initial reference voltage of the MOSFET.The avalanche current block IGEN, the avalanche resistance block RSUB, and parasitic BJT block PBJT could utilize existent model parameters and describe the “avalanche breakdown”.After coding all the five blocks using Verilog-A, import them into Cadence and then construct the whole circuit-level model.
4. Results
The macro model can simulate the “cond breakdown” action under ESD overstress. As is shown in Fig. 7, we
connect the Gate, Source and Body to the Ground and connect Drain to the I/O pad. The DC current source I is ud to sweep the ESD currents.
Fig.7 Circuits for Simulation
As is shown in Fig. 8, the current source sweeps from 0A to 3.5A, the macro model will undergo the “avalanche breakdown” and the “cond breakdown” one after another. The trigger voltage is at 7.49V, with the current 1mA; the holding voltage after snapback is 4.91V; the cond breakdown current is 2.39A with the voltage 6.01V; the voltage after the cond breakdown is 955mV. When the
MOSFET enter the avalanche breakdown, if the power injected into the device is removed, the device will not be destroyed and could return to normal. But after the cond breakdown happens, the MOSFET will be damaged and can never be recovered.
The trigger voltage and holding voltage at the avalanche breakdown are mainly decided by the avalanche multiplier M in the avalanche current block IGEN, which can be extracted by TCAD simulation. The on resistance between two breakdowns Ron can be decided by the modulation resistor Rd. The voltage and current at the cond breakdown is dependent on the size of the MOSFET and the dopant concentration at drain and Pwell.
The physical mechanism of the cond breakdown can be correctly reflected using the parameter definition in this macro model. This model also owns the advantages of high speed, fine accuracy and convergency.
Fig.8 Simulation Results in Spectre of Cadence 5.Conclusion
Bad on deep understand of the physical mechanism of the cond breakdown, a macro model to describe the cond breakdown of MOSFETs under ESD overstress using a thermal nsitive block Switch and a thermal resistance block Rthermal, is prented in this paper. This macro model has fine accuracy and convergency and has important meaning to circuit-level or system-level simulation of the ability of ESD protection networks.
References
1. X. Y. Zhang, “Modeling and Characterization of Substrate
Resistance for Deep Submicron ESD Protection Devices,”
Stanford University, August 2002.
2. X. F. Gao, J. J. Liou, A. Ortiz-Conde, J. Bernier, and G.
Croft, “A physics-bad model for the substrate resistance of MOSFET’s,” Solid-State Electrons., vol. 46, (2002), pp 853–857
3. Amitabh Chatterjee, et al., “New Physical Insight and
Modeling of Second Breakdown(It2) Phenomenon in Advanced ESD Protection Devices,” Electron Devices Meeting, 2005. IEDM Technical Digest. Dec. 2005 ,pp 195 – 198.
4. Hillkirk, L.M et al,” Investigation of thermal breakdown
mechanism in 0. 13 /spl mu/m technology ggNMOS under ESD conditions,”Simulation of Semiconductor Process and Devices, 2003. SISPAD 2003. International Conference on 3-5 , Sept. 2003, pp 125 - 128
5. Diaz, C.H et al,” Circuit-level electrothermal simulation of
electrical overstress failures in advanced MOS I/O protection devices ,”Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 13, Issue 4, April 1994, pp 482 – 493
6. Ajith Amerakera, et al., “Characterization and Modeling
of Second Breakdown in NMOST’s for the Extraction of ESD-Related Process and Design Parameters,”IEEE Transactions on Electro Devices, Vol. 38, No.9, Sep.
1991, pp 2161-2168.
