2N7002W-D_N-Channel Enhancement Mode Field Effect Transistor

更新时间:2023-05-16 00:05:09 阅读: 评论:0

2N7002W, 2V7002W
Small Signal MOSFET
刀光剑影的意思60 V, 340 mA, Single, N−Channel, SC−70 Features
•ESD Protected
•Low R DS(on)
•Small Footprint Surface Mount Package
•The Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant
•2V Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable
Applications
•Low Side Load Switch
•Level Shift Circuits
•DC−DC Converter
•Portable DSC, PDA, Cell Phone, etc. MAXIMUM RATINGS  (T J = 25°C unless otherwi stated)
Rating Symbol Value Unit Drain−to−Source Voltage V DSS60V Gate−to−Source Voltage V GS±20V
Drain Current (Note 1)
Steady State T A = 25°C
T A = 85°C
t < 5 s T A = 25°C
T A = 85°C I D
310
220
340
240
mA
Power Dissipation (Note 1) Steady State
t < 5 s P D
280
330
mW
Puld Drain Current (t p = 10 m s)I
DM  1.4A
Operating Junction and Storage Temperature Range T J, T STG−55 to
+150
°C
Source Current (Body Diode)I S250mA Lead Temperature for Soldering Purpos
(1/8″ from ca for 10 s)
T L260°C
Gate−Source ESD Rating
(HBM, Method 3015)
ESD900V
Stress exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings
only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stress above the Recommended Operating Conditions may affect device reliability. THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit Junction−to−Ambient − Steady State
(Note
1)R q JA450°
C/W
Junction−to−Ambient − t ≤ 5 s (Note 1)R q JA375
1.Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in
g20成员国sq [1 oz] including traces)
Device Package Shipping†
ORDERING INFORMATION
2N7002WT1G3000/T ape & Reel SIMPLIFIED SCHEMATIC
SC−70/SOT−323
CASE 419
STYLE 8
71 M G
G
71= Device Code
M= Date Code
G= Pb−Free Package
MARKING DIAGRAM
& PIN ASSIGNMENT
3
2
1
Drain
Gate Source
怎么折玫瑰花
SC−70
(Pb−Free)
60 V  1.6 W @ 10 V
R DS(on) MAX
340 mA
I D MAX
(Note 1)
V(BR)DSS
†For information on tape and reel specifications, including part orientation and tape sizes, plea refer to our T ape and Reel Packaging Specifications Brochure, BRD8011/D.
2.5 W @ 4.5 V
Gate
Source
Drain
(Top View)
(Note: Microdot may be in either location)
2V7002WT1G3000/T ape & Reel
SC−70
(Pb−Free)
ELECTRICAL CHARACTERISTICS (T J = 25°C unless otherwi specified)
Parameter Symbol Test Condition Min Typ Max Units OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS V GS = 0 V, I D = 250 m A60V Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/T J71mV/°C
Zero Gate Voltage Drain Current I DSS V
GS = 0 V,
V DS = 60 V T J = 25°C  1.0m A T J = 150°C15m A
组长的拼音V GS = 0 V, V DS = 50 V T J = 25°C100n A T J = 150°C10m A
Gate−to−Source Leakage Current I GSS V DS = 0 V, V GS = ±20 V±10m A
V DS = 0 V, V GS = ±10 V450nA
V DS = 0 V, V GS = ±5.0 V150nA ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage V GS(TH)V GS = V DS, I D = 250 m A  1.0  2.5V Negative Threshold Temperature
Coefficient
V GS(TH)/T J  4.0mV/°C Drain−to−Source On Resistance R DS(on)V GS = 10 V, I D = 500 mA  1.19  1.6W
V GS = 4.5 V, I D = 200 mA  1.33  2.5
Forward Transconductance g FS V DS = 5 V, I D = 200 mA530mS CHARGES AND CAPACITANCES
Input Capacitance C ISS
V GS = 0 V, f = 1 MHz,
V DS = 20 V 24.5pF
Output Capacitance C OSS  4.2 Rever Transfer Capacitance C RSS  2.2
Total Gate Charge Q G(TOT)
V GS = 4.5 V, V DS = 10 V;
I D = 200 mA 0.7nC
Threshold Gate Charge Q G(TH)0.1 Gate−to−Source Charge Q GS0.3 Gate−to−Drain Charge Q GD0.1 SWITCHING CHARACTERISTICS, V GS =  V (Note 3)
Turn−On Delay Time t d(ON)
V GS = 10 V, V DD = 25 V,
I D = 500 mA, R G = 25 W 12.2ns
Ri Time t r9.0 Turn−Off Delay Time t d(OFF)55.8 Fall Time t f29 DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage V SD V
GS = 0 V,
I S = 200 mA T J = 25°C0.8  1.2V T J = 85°C0.7
2.Pul Test: pul width ≤ 300 m s, duty cycle ≤ 2%
3.Switching characteristics are independent of operating junction temperatures
Figure 1. On −Region Characteristics
梦见自己尿尿Figure 2. Transfer Characteristics
V DS , DRAIN −TO −SOURCE VOLTAGE (V)V GS , GATE −TO −SOURCE VOLTAGE (V)
Figure 3. On −Resistance vs. Drain Current and
Temperature
Figure 4. On −Resistance vs. Drain Current and
氧化铌
Temperature
I D , DRAIN CURRENT (A)Figure 5. On −Resistance vs. Gate −to −Source
Voltage Figure 6. On −Resistance Variation with
Temperature
V GS , GATE −TO −SOURCE VOLTAGE (V)T J , JUNCTION TEMPERATURE (°C)
I D , D R A I N  C U R R E N T  (A )
I D , D R A I N  C U R R E N T  (A )
酒酣胸胆尚开张
R D S (o n ), D R A I N −T O −S O U R C E  R E S I S T A N C E  (W )
R D S (o n ), D R A I N −T O −S O U R C E  R E S I S T A N C E  (W )
R D S (o n ), D R A I N −T O −S O U R C E R E S I S T A N C E  (N O R M A L I Z E D )
I D , DRAIN CURRENT (A)
R D S (o n ), D R A I N −T O −S O U R C E  R E S I S T A N C E  (W )
Figure 7. Capacitance Variation
Figure 8. Gate −to −Source and
Drain −to −Source Voltage vs. Total Charge
Qg, TOTAL GATE CHARGE (nC)
Figure 9. Diode Forward Voltage vs. Current
V SD , SOURCE −TO −DRAIN VOLTAGE (V)
V G S , G A T E −T O −S O U R C E  V O L T A G E  (V )
I S , S O U R C E  C U R R E N T  (A )
C , C A P A C I T A N C E英勇无敌
(p F )
GATE −TO −SOURCE OR DRAIN −TO −SOURCE VOLTAGE (V)1.0E −10
1.0E −9
1.0E −8
1.0E −6
51015202530Figure 10. Drain −to −Source Leakage Current
vs. Voltage
V DS , DRAIN −TO −SOURCE VOLTAGE (V)
I D S S , L E A K A G E  (A )
354045505560
1.0E −7
PACKAGE DIMENSIONS
SC −70 (SOT −323)CASE 419−04ISSUE M
NOTES:
1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198
2.
2.CONTROLLING DIMENSION: INCH.
DIM A MIN NOM MAX MIN
MILLIMETERS
0.800.90  1.000.032INCHES A10.000.050.100.000A20.7 REF b 0.300.350.400.012c 0.100.180.250.004D    1.80  2.10  2.200.071E    1.15  1.24  1.350.045e    1.20  1.30  1.400.0470.0350.0400.0020.0040.0140.0160.0070.0100.0830.0870.0490.0530.0510.055NOM MAX L    2.00
2.10  2.40
0.079
0.083
0.095
H E
e10.65 BSC 0.425 REF 0.028 REF 0.026 BSC 0.017 REF STYLE 8:
PIN 1.GATE  2.SOURCE  3.DRAIN
ǒmm inches
ǓSCALE 10:1
*For additional information on our Pb −Free strategy and soldering
details, plea download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ON Semiconductor  and          are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).  SCILLC owns the rights to a number of patents, trademarks,copyrights, trade crets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accesd i.com/site/pdf/Patent −Marking.pdf.  SCILLC rerves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, reprentation or guarantee regarding the suitability of its products for any particular purpo, nor does SCILLC assume any liability arising out of the application or u of any product or circuit, and specifically disclaims any and all liability, including without limitation special, conquential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating p
arameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any licen under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for u as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purcha or u SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens, and reasonable attorney fees arising out of, directly or indirectly,any claim of personal injury or death associated with such unintended or unauthorized u, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION

本文发布于:2023-05-16 00:05:09,感谢您对本站的认可!

本文链接:https://www.wtabcd.cn/fanwen/fan/89/901398.html

版权声明:本站内容均来自互联网,仅供演示用,请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系,我们将在24小时内删除。

标签:组长   梦见   拼音   尿尿
相关文章
留言与评论(共有 0 条评论)
   
验证码:
推荐文章
排行榜
Copyright ©2019-2022 Comsenz Inc.Powered by © 专利检索| 网站地图