REV. PrC 24/05/02
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
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a
A D7451/AD7441
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 Fax: 781/326-8703© Analog Devices, Inc., 2002
Pudo Differential, 1MSPS,
12- & 10-Bit ADCs in 8-lead SOT-23
FEATURES
Fast Throughput Rate: 1MSPS
Specified for V DD of 2.7 V to 5.25 V Low Power at max Throughput R ate:3.75 mW typ at 1MSPS with V DD = 3 V 9 mW typ at 1MSPS with V DD = 5 V Pudo Differential Analog Input Wide Input Bandwidth:
70dB SINAD at 300kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays
High Speed Serial Interface - SPI TM /QSPI TM /MICROWIRE TM / DSP Compatible Power-Down Mode: 1µA max
8 Pin SOT-23 and µSOIC Packages A P P L I C A T I O N S
Transducer Interface Battery Powered Systems Data Acquisition Systems Portable Instrumentation Motor Control
C o m m u n i c a t i o n s
GENER AL DESCR IPTION
The AD7451/AD7441 are respectively 12- and 10-bit,high speed, low power, successive-approximation (SAR)analog-to-digital converters that feature a pudo differen-tial analog input. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1MSPS.
The parts contains a low-noi, wide bandwidth, differen-tial track and hold amplifier (T/H) which can handle input frequencies in excess of 1MHz with the -3dB point being 20MHz typically. The reference voltage is 2.5 V and is applied externally to the V REF pin.
The conversion process and data acquisition are controlled using CS and the rial clock allowing the device to inter-face with Microprocessors or DSPs. The input signals are sampled on the falling edge of CS and the conversion is also initiated at this point.
The SAR architecture of the parts ensures that there are no pipeline delays.
FUNCTIONAL BLOCK DIAGR AM
The AD7451/41 u advanced design techniques to achieve very low power dissipation at high throu
ghput rates.
PR ODUCT HIGHLIGHTS
1.Operation with
2.7 V to 5.25 V power supplies.2.High Throughput with Low Power Consumption.With a 3V supply, the AD7451/41 offer
3.75mW typ power consumption for 1MSPS throughput.3.Pudo Differential Analog Input.
The V IN- input can be ud as an offt from ground 4.Flexible Power/Serial Clock Speed Management.The conversion rate is determined by the rial clock,allowing the power to be reduced as the conversion time is reduced through the rial clock speed increa. The parts also feature a shutdown mode to maximize power efficiency at lower throughput rates.5.No Pipeline Delay.
6.Accurate control of the sampling instant via a CS input and once off conversion control.
MICROWIRE is a trademark of National Semiconductor Corporation.SPI and QSPI are trademarks of Motorola, Inc.
V V V V 元器件交易网
REV. PrC
PRELIMINARY TECHNICAL DATA
–2–Parameter
Test Conditions/Comments B Version 1
Unit
DYNAMIC PERFORMANCE Signal to (Noi + Distortion)(SINAD)2
70dB min Total Harmonic Distortion (THD)2-80dB typ -75dB max Peak Harmonic or Spurious Noi 2-82dB typ
-75dB max Intermodulation Distortion (IMD)2Second Order Terms -85dB typ Third Order Terms -85dB typ Aperture Delay 210ns typ Aperture Jitter 2
50ps typ Full Power Bandwidth 2
@ -3 dB 20MHz typ @ -0.1 dB
2.5MHz typ DC ACCURACY Resolution
12Bits
Integral Nonlinearity (INL)2
±1
LSB max Differential Nonlinearity (DNL)2G uaranteed No Misd Codes to 12 Bits.
±1LSB max Offt Error 2关于酒的诗
±3LSB max G ain Error 2
±3LSB max ANALOG INPUT Full Scale Input Span V IN+ - V IN-
V REF V Absolute Input Voltage V IN+V REF
V V IN-3
0.1 to 1V
DC Leakage Current ±1µA max Input Capacitance When in Track 20pF typ When in Hold 6
pF typ
REFERENCE INPUT V REF Input Voltage ±1% tolerance for specified performance
2.5V
DC Leakage Current ±1µA max V REF Input Capacitance 15pF typ LOG IC INPUTS
Input High Voltage, V INH 2.4V min Input Low Voltage, V INL 0.8V max Input Current, I IN
Typically 10nA, V IN = 0VorV DD
±1µA max Input Capacitance, C IN 410pF max LOG IC OUTPUTS
Output High Voltage, V OH
V DD = 5V; I SOURCE = 200µA 2.8V min V DD = 3V; I SOURCE = 200µA 2.4V min Output Low Voltage, V OL
I SINK =200µA
0.4V max Floating-State Leakage Current ±1µA max Floating-State Output Capacitance 410
pF max
Output Coding
Straight (Natural)Binary
齐驱AD7451 - SPECIFICATIONS
1
( V DD = 2.7V to 5.25V, f SCLK = 18MHz, f S = 1MHz, V REF = 2.5 V; F IN = 300kHz;T A = T MIN to T MAX , unless otherwi noted.)
元器件交易网
REV. PrC PRELIMINARY TECHNICAL DATA
–3–
A D7451/AD7441
Parameter
Test Conditions/Comments
B Version 1 Units CONVERSION RATE Conversion Time
888ns with an 18MHz SCLK 16SCLK cycles Track/Hold Acquisition Time 2Sine Wave Input 200ns max Step Input
TBD
TBD ns max Throughput Rate 6
1MSPS max POWER REQUIREMENTS V D D 2.7/5.25
Vmin/max I DD 5,7
Normal Mode(Static)
SCLK On or Off 0.5mA typ Normal Mode (Operational)V DD = 5 V. 1.8mA max V DD = 3 V.
可爱表情简笔画
1.25mA max Full Power-Down Mode SCLK On or Off
1µA max Power Dissipation
Normal Mode (Operational)V DD =5 V.9mW max V DD =3 V.
3.75mW max Full Power-Down
V DD =5 V. SCLK On or Off 5µW max V DD =3 V. SCLK On or Off
3
µW max
N O T E S 1
Temperature ranges as follows: B Versions: –40°C to +85°C.2
鞋用英语怎么说
See ‘Terminology’ ction.3
A small DC input is applied to V IN- to provide a pudo ground for V IN+4
Sample tested @ +25°C to ensure compliance.5
See POWER VERSUS THROUG HPUT RATE ction.6
See ‘Serial Interface Section’.7
Measured with a midscale DC input.
Specifications subject to change without notice.
AD7451 - SPECIFICATIONS
1
元器件交易网
REV. PrC
PRELIMINARY TECHNICAL DATA
–4–Parameter
Test Conditions/Comments B Version 1
Unit
DYNAMIC PERFORMANCE Signal to (Noi + Distortion)(SINAD)2
61dB min Total Harmonic Distortion (THD)2-80dB typ -73dB max Peak Harmonic or Spurious Noi 2-82dB typ
-73dB max Intermodulation Distortion (IMD)2Second Order Terms -78dB typ Third Order Terms -78dB typ Aperture Delay 210ns typ Aperture Jitter 2
50ps typ Full Power Bandwidth 2
@ -3 dB 20MHz typ @ -0.1 dB
2.5MHz typ DC ACCURACY Resolution
10Bits
Integral Nonlinearity (INL)2
±0.5
LSB max Differential Nonlinearity (DNL)2G uaranteed No Misd Codes to 10 Bits.
±0.5LSB max Offt Error 2
±3LSB max G ain Error 2
±3LSB max ANALOG INPUT Full Scale Input Span V IN+ - V IN-
V REF V Absolute Input Voltage V IN+V REF
V V IN-3
0.1 to 1V
DC Leakage Current ±1µA max Input Capacitance When in Track 20pF typ When in Hold
6
pF typ
REFERENCE INPUT V REF Input Voltage ±1% tolerance
for specified performance
2.5V
DC Leakage Current ±1µA max V REF Input Capacitance 15pF typ LOG IC INPUTS
Input High Voltage, V INH 2.4V min Input Low Voltage, V INL 0.8V max Input Current, I IN
Typically 10nA, V IN = 0VorV DD
±1µA max Input Capacitance, C IN 410pF max LOG IC OUTPUTS
Output High Voltage, V OH
V DD = 5V; I SOURCE = 200µA 2.8V min V DD = 3V; I SOURCE = 200µA 2.4V min Output Low Voltage, V OL
I SINK =200µA
0.4V max Floating-State Leakage Current ±1µA max Floating-State Output Capacitance 410
牛奶冰淇淋pF max
Output Coding
Straight (Natural)Binary
AD7441 - S PECIFICATIO NS
1
( V DD = 2.7V to 5.25V, f SCLK = 18MHz, f S = 1MHz, V REF = 2.5 V; F IN = 300kHz;T A = T MIN to T MAX , unless otherwi noted.)
元器件交易网
REV. PrC PRELIMINARY TECHNICAL DATA
–5–
A D7451/AD7441
Parameter
Test Conditions/Comments
B Version 1 Units CONVERSION RATE Conversion Time
888ns with an 18MHz SCLK 16SCLK cycles Track/Hold Acquisition Time 2Sine Wave Input 200ns max Step Input
TBD ns max Throughput Rate 6
1MSPS max POWER REQUIREMENTS V D D 2.7/5.25
Vmin/max I DD 6,7
蛋皮的家常做法Normal Mode(Static)
SCLK On or Off 0.5mA typ Normal Mode (Operational)V DD = 5 V. 1.8mA max V DD = 3 V.
1.25mA max Full Power-Down Mode SCLK On or Off
1µA max Power Dissipation
Normal Mode (Operational)V DD =5 V.9mW max V DD =3 V.
3.75mW max Full Power-Down
V DD =5 V. SCLK On or Off 5µW max V DD =3 V. SCLK On or Off
3
µW max
N O T E S 1
Temperature ranges as follows: B Versions: –40°C to +85°C.2
See ‘Terminology’ ction.3
A small DC input is applied to V IN- to provide a pudo ground for V IN+4
Sample tested @ +25°C to ensure compliance.5
See POWER VERSUS THROUG HPUT RATE ction.6
See ‘Serial Interface Section’.7综上所述的英文
Measured with a midscale DC input.
Specifications subject to change without notice.
AD7441 - S PECIFICATIO NS 1
元器件交易网
REV. PrC
PRELIMINARY TECHNICAL DATA
–6–
Limit at
Parameter T MIN , T MAX Units Description
龙虾的做法f SCLK 410 kHz min 18
MHz max t CONVERT 16 x t SCLK t SCLK = 1/f SCLK
888ns max t QUIET 25ns min Minimum Quiet Time between the End of a Serial Read and the Next Falling Edge of CS t 110ns min Minimum CS Pulwidth
t 210ns min CS falling Edge to SCLK Falling Edge Setup Time
t 3520ns max Delay from CS Falling Edge Until SDATA 3-State Disabled t 4540
ns max Data Access Time After SCLK Falling Edge t 50.4 t SCLK ns min SCLK High Pul Width t 60.4 t SCLK ns min SCLK Low Pul Width
t 710ns min SCLK Edge to Data Valid Hold Time
t 86
10ns min SCLK Falling Edge to SDATA 3-State Enabled 35ns max SCLK Falling Edge to SDATA 3-State Enabled t POWER-UP 7
1
µs max
Power-Up Time from Full Power-Down
N O T E S 1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD ) and timed from a voltage level of 1.6 Volts.2
See Figure 1, Figure 2 and the ‘Serial Interface’ ction.3
Common Mode Voltage.4
Mark/Space ratio for the SCLK input is 40/60 to 60/40.5
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V and time for an output to cross 0.4 V or 2.0 V for V DD = 3 V.6
t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured num-ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.7
See ‘Power-up Time’ Section.
TIMING SPECIFICATIONS 1,2
( V DD = 2.7V to 5.25V, f SCLK = 18MHz, f S = 1MHz, V REF = 2.5 V; F IN = 300kHz;T A = T MIN to T MAX , unless otherwi noted.)
Figure 2. AD7441 Serial Interface Timing Diagram
AD7451/AD7441
4LEADING ZERO’S 2TRAILING ZEROS
元器件交易网
