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a
AD9012
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High Speed 8-Bit TTL A/D Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
100 MSPS ENCODE Rate
Very Low Input Capacitance—16 pF Low Power—1 W
TTL Compatible Outputs
MIL-STD-883 Compliant Versions Available APPLICATIONS Radar Guidance
Digital Oscilloscopes/ATE Equipment Lar/Radar Warning Receivers Digital Radio
Electronic Warfare (ECM, ECCM, ESM)Communication/Signal Intelligence
GENERAL DESCRIPTION
The AD9012 is an 8-bit, ultrahigh speed, analog-to-digital converter. The AD9012 is fabricated in an advanced bipolar process that allows operation at sampling rates up to 100megasamples/cond. Functionally, the AD9012 is comprid of 256 parallel comparator stages who outputs are decoded to drive the TTL compatible output latches.
The exceptionally wide large-signal analog input bandwidth of 160 MHz is due to an innovative comparator design and very clo attention to device layout considerations. The wide input bandwidth of the AD9012 allows very accurate acquisition of high speed pul inputs without an external track-and-hold.The comparator output decoding scheme minimizes fal codes,which is critical to high speed linearity.
The AD9012 is available in two grades: one with 0.5 LSB linearity and one with 0.75 LSB linearity. B
oth versions are
offered in an industrial grade, –25°C to +85°C, packaged in a 28-lead DIP and a 28-lead JLCC. The military temperature range devices, –55°C to +125°C, are available in ceramic DIP and LCC packages and are compliant to MIL-STD-883 Class B.The AD9012 is available in versions compliant with MIL-STD-883.Refer to the Analog Devices Military Products Databook or current AD9012/883B data sheet for detailed specifications.
AD9012–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+V S = +5.0 V; –V S = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwi noted.)
Test AD9012AQ/AJ AD9012BQ/BJ AD9012SQ/SE AD9012TQ/TE Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION8888Bits DC ACCURACY
Differential Linearity25°C I0.60.750.40.50.60.750.40.5LSB
Full VI 1.00.75 1.00.75LSB Integral Linearity25°C I0.6 1.00.40.50.6 1.00.40.5LSB
Full VI 1.2 1.2 1.2 1.2LSB No Missing Codes Full VI Guaranteed Guaranteed Guaranteed Guaranteed
INITIAL OFFSET ERROR
Top of Reference Ladder25°C I715715715715mV
Full VI18181818mV Bottom of Reference Ladder25°C I610610610610mV
Full VI13131313mV Offt Drift Coefficient Full V25252525µV/°C ANALOG INPUT
Input Bias Current125°C I60200602006020060200µA
Full VI200200200200µA Input Resistance25°C I25200252002520025200kΩInput Capacitance25°C III1618161816181618pF Large Signal Bandwidth225°C V160160160160MHz Analog Input Slew Rate325°C V440440440440V/µs REFERENCE INPUT
Reference Ladder Resistance25°C VI4080110408011040801104080110ΩLadder Temperature Coefficient V0.250.250.250.25Ω/°C Reference Input Bandwidth25°C V10101010MHz DYNAMIC PERFORMANCE
不知疲倦
Conversion Rate25°C I75100751007510075100MSPS Aperture Delay25°C V 3.8 3.8 3.8 3.8ns Aperture Uncertainty (Jitter)25°C V15151515ps Output Delay (t PD)4, 525°C I4 4.9114 4.9114 4.9114 4.911ns Transient Respon625°C V8888ns Overvoltage Recovery Time725°C V8888ns Output Ri Time425°C I 6.68.0 6.68.0 6.68.0 6.68.0ns Output Fall Time425°C I 3.3 4.3 3.3 4.3 3.3 4.3 3.3 4.3ns Output Time Skew4, 825°C V 3.0 3.0 3.0 3.0ns ENCODE INPUT
Logic “1” Voltage4Full VI 2.0 2.0 2.0 2.0V Logic “0” Voltage4Full VI0.80.80.80.8V Logic “1” Current Full VI250250250250µA Logic “0” Current Full VI400400400400µA Input Capacitance25°C V 2.5 2.5 2.5 2.5pF ENCODE Pulwidth (Low)925°C I 2.5 2.5 2.5 2.5ns ENCODE Pulwidth (High)925°C I 2.5 2.5 2.5 2.5ns OVERFLOW INHIBIT INPUT
0 V Input Current Full VI200250200250200250200250µA
AC LINEARITY10
Effective Bits1125°C V7.57.57.57.5Bits In-Band Harmonics
DC to 1.23 MHz25°C I4855485548554855dBc DC to 9.3 MHz25°C V50505050dBc DC to 19.3 MHz25°C V44444444dBc Signal-to-Noi Ratio1225°C I4647.64647.64647.64647.6dBc Noi Power Ratio1325°C V37373737dBc DIGITAL OUTPUT
Logic “1” Voltage Full VI 2.4 2.4 2.4 2.4V Logic “0” Voltage Full VI0.40.40.40.4V POWER SUPPLY14
Positive Supply Current (+5.0 V)25°C I3345334533453345mA
Full VI48484848mA Supply Current (–5.2 V)25°C I152179152179152179152179mA
Full VI191191191191mA Nominal Power Dissipation25°C V955955955955mW Reference Ladder Dissipation25°C V44444444mW Power Supply Rejection Ratio1525°C I0.85 2.50.85 2.50.8 2.50.8 2.5mV/V
–2–
REV. F
REV. F AD9012
–3–
CAUTION
ESD (electrostatic discharge) nsitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9012 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
NOTES 1
Measured with analog input = 0 V.2
Measured by FFT analysis where fundamental is –3 dBc.3
Input slew rate derived from ri time (10% to 90%) of full-scale step input.4
Outputs terminated with two equivalent ’LS00 type loads. (See load circuit.)5
Measured from ENCODE into data out for LSB only.6
For full-scale step input, 8-bit accuracy is attained in specified time.7
Recovers to 8-bit accuracy in specified time, after 150% full-scale input overvoltage.8
Output time skew includes high-to-low and low-to-high transitions as well a s bit-to-bit time skew differences.
9
ENCODE signal ri/fall times should be less than 30 ns for normal operation.
10Measured at 75 MSPS ENCODE rate. Harmonic data bad on worst-ca harmonics.11
Analog input frequency = 1.23 MHz.12
RMS signal to rms noi, including harmonics with 1.23 MHz. Analog input signal.13
NPR measured @ 0.5 MHz. Noi source is 250 mW (rms) from 0.5 MHz to 8 MHz.14
Supplies should remain stable within ±5% for normal operation.15
Measured at –5.2 V ±5% and +5.0 V ±5%.Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
Positive Supply Voltage (+V S ).. . . . . . . . . . . . . . . . . . . . . 6 V Analog to Digital Supply Voltage Differential (–V S ) . . . 0.5 V
Negative Supply Voltage (–V S ) .
. . . . . . . . . . . . . . . . . . . –6 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . –V S to +0.5 V ENCODE Input Voltage . . . . . . . . . . . . . . . . . –0.5 V to +5 V OVERFLOW INH Input Voltage . . . . . . . . . . . –5.2 V to 0 V Reference Input Voltage (+V REF , –V REF )2 . . –3.5 V to +0.1 V Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . 2.1 V Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . ±4 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Operating Temperature Range
AD9012AQ/BQ/AJ/BJ . . . . . . . . . . . . . . . –25°C to +85°C AD9012SE/SQ/TE/TQ . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature 3 . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead Soldering Temperature (10 c) . . . . . . . . . . . . . 300°C
NOTES 1
Absolute Maximum Ratings are limiting values, to be applied individually, and beyond which the rviceability of the circuit may be impaired. Functional operability under any of the conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.2
+V REF ≥ –V REF under all circumstances.3
Maximum junction temperature (T J max) should not exceed 150°C for ceramic and plastic packages:T J = PD (θJA ) + T A PD (θJC ) + Tc where:
PD = power dissipation
θJA = thermal impedance from junction to ambient (°C/W)θJC = thermal impedance from junction t
o ca (°C/W)T A = ambient temperature (°C)T C = ca temperature (°C)Typical thermal impedances are:
Ceramic DIP θJA = 42°C/W; θJC = 10°C/W Ceramic LCC θJA = 50°C/W; θJC = 15°C/W JLCC θJA = 59°C/W; θJC = 15°C/W
国军抗日Recommended Operating Conditions
Input Voltage (V)
Parameter Min Nominal
Max –V S –5.46–5.20–4.94+V S +4.75+5.00+5.25+V REF –V REF 0.0+0.1–V REF
–2.1–2.0
+V REF Analog Input
–V REF
+V
REF
Figure 1.Load Circuit
EXPLANATION OF TEST LEVELS Test Level
I –100% production tested.
II –100% production tested at 25°C, and sample tested at
specified temperatures. AC testing done on sample basis.III –Sample tested only.
IV –Parameter is guaranteed by design and characterization
testing.V –Parameter is a typical value only.
VI –All devices are 100% production tested at 25°C. 100%
production tested at temperature extremes for extended temperature devices; guaranteed by design and characterization testing for industrial devices.
ORDERING GUIDE
Temperature Package Device Linearity Ranges
Options *AD9012AQ 0.75 LSB –25°C to +85°C Q-28AD9012BQ 0.50 LSB –25°C to +85°C Q-28AD9012AJ 0.75 LSB –25°C to +85°C J-28A AD9012BJ 0.50 LSB –25°C to +85°C J-28A AD9012SQ 0.75 LSB –55°C to +125°C Q-28AD9012SE 0.75 LSB –55°C to +125°C E-28A AD9012TQ 0.50 LSB –55°C to +125°C Q-28AD9012TE
0.50 LSB
–55°C to +125°C
E-28A
*E = Leadless Ceramic Chip Carrier; J = Ceramic Leaded Chip Carrier;Q = Cerdip.
REV. F
AD9012
–4–
PIN FUNCTION DESCRIPTIONS
Pin No.Mnemonic Description
11DIGITAL +V S
One of Three Positive Digital Supply Pins (Nominally 5.0 V)
12
OVERFLOW INH
OVERFLOW INH BIT controls the data output coding for overvoltage inputs (AIN ≥ + V REF ).
3HYSTERESIS The hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a change from –5.2 V to –2.2 V at the hysteresis control pin.
14+V REF
The Most Positive Reference Voltage for the Internal Resistor Ladder
15ANALOG INPUT One of Two Analog Input Pins. Both analog input pins should be connected together.16ANALOG GROUND One of Two Analog Ground Pins. Both analog ground pins should be connected together.17ENCODE TTL Level ENCODE Command Input. ENCODE is rising edge nsitive.18DIGITAL +V S
One of Three Positive Digital Supply Pins (Nominally +5.0 V)
19ANALOG GROUND One of Two Analog Ground Pins. Both analog ground pins should be connected together.10ANALOG INPUT One of Two Analog Input Pins. Both analog inputs should be connected together.11–V REF The Most Negative Reference Voltage for the Internal Resistor Ladder 12REF MID
The Midpoint Tap on the Internal Resistor Ladder
13DIGITAL +V S One of Three Positive Digital Supply Pins (Nominally +5.0 V)
14DIGITAL –V S
One of Two Negative Digital Supply Pins (Nominally –5.2 V). Both digital supply pins should be connected together.
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15D 1 (LSB)Digital Data Output. D 1 (LSB) is the least significant bit of the digital output word.16–19D 2–D 5
Digital Data Output
20DIGITAL GROUND One of Two Digital Ground Pins. Both digital grounds pins should be connected together.
21, 22ANALOG –V S
One of Two Negative Analog Supply Pins (Nominally –5.2 V). Both analog supply pins should be connected together.
23DIGITAL GROUND One of Two Digital Ground Pins. Both digital ground pins should be connected together.24, 25D 6, D 7
Digital Data Output
26D 8 (MSB)Digital data output D 8 (MSB) is the most significant bit of the digital output word.27OVERFLOW Overflow Data Output. Logic HIGH indicates an input overvoltage (V IN > + V REF ) if OVERFLOW INH is enabled (overflow enabled, floating). See OVERFLOW INH.
28
DIGITAL –V S
One of Two Negative Digital Supply Pins (Nominally –5.2 V). Both digital supply pins should be connected together.
PIN CONFIGURATIONS
DIGITAL +V S REF MID –V REF ANALOG INPUT ANALOG GROUND
DIGITAL +V S
DIGITAL +V S
OVERFLOW INH HYSTERESIS
英语助动词+V REF
ENCODE ANALOG GROUND
ANALOG INPUT D 1
(LSB)D 2D 3D 4D 5DIGITAL GROUND ANALOG –V S
DIGITAL –V S
OVERFLOW
D 8 (MSB)D 7ANALOG –V S
DIGITAL GROUND D 6
DIGITAL –V S D 7
D 6
DIGITAL GROUND ANALOG –V S ANALOG –V S D 5
ANALOG INPUT ANALOG GROUND ENCODE DIGITAL +V S ANALOG INPUT –V REF +V R E F
H Y S T E R E S I S
O V E R F L O W I N H D I G I T A L +V S
D I G I T A L –V S
O V E R F L O W
D 8 (M S B )
R E F M I D
D I G I T A L +V S
D I G I T A L –V S
D 1 (L S B )D 2
D 3D 4
DIGITAL GROUND ANALOG GROUND t u p n I g o l a n A )g n i t a o l F (d e l b a n E w o l f r e v O D f o 1D 2D 3D 4D 5D 6D 7D 8w o l f r e v O )D N G (d e t i b i h n I f o D 1D 2D 3D 4D 5D 6D 7D 8V N I V +F E R 0000000011
11
劳动协议书范本111110V N I V +<F
E R X
X X X X X X X 0X
X X X X X X X 0
REV. F –5–
AD9012
Figure 2.Timing Diagram
ENCODE
DIGITAL OUTPUTS
Figure 3.Input Output Circuits
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . 111 mils × 123 mils × 15 mils (±2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils × 4 mils Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V S Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Epoxy (Plastic)Bond Wire . . . . . . . . 1 mil to 1.3 mil Gold; Gold Ball Bonding
ALL RESISTORS ؎5%ALL CAPACITORS ؎20%
ALL SUPPLY VOLTAGES ؎5%
AD1
AD2–2.0V
OPTION #1 (STATIC) AD1 = –2.0V; AD2 = +2.4V OPTION #2 (DYNAMIC) SEE WAVEFORMS
0V –2V AD1
AD2
Figure 4.Burn-In Diagram
REV. F
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AD9012
–6–APPLICATION INFORMATION
The AD9012 is compatible with all standard TTL logic families.However, to operate at the highest ENCODE rates, the sup-porting logic around the AD9012 will need to be equally fast.Two possible choices are the AS and the ALS families. Which-ever of the TTL logic families is ud, special care must be exercid to keep digital switching noi away from the analog circuits around the AD9012. The two most critical items are the digital supply lines and the digital ground return.
The input capacitance of the AD9012 is an exceptionally low 16 pF. This allows the u of a wide range of input amplifiers,both hybrid and monolithic. To take full advantage of the 160 MHz input bandwidth of the AD9012, a hybrid amplifier such as the AD9610 will be required. For tho applications that do not require the full input bandwidth of the AD9012, some of the more traditional monolithic amplifiers, such as the AD846,should work very well. Overall performance with monolithic amplifiers can be improved by inrting a 40 Ω resistor in ries with the amplifier output.
The output data is buffered through the TTL compatible out-put latches. In addition to the latch propagation delay (t PD ), all data is delayed by one clock cycle before becoming available at the outputs. Both the analog-to-digital conversion cycle and the data transfer to the output latches are triggered on the rising edge of the TTL compatible ENCODE signal (e Figure 2).The AD9012 also incorporates a HYSTERESIS control pin that provides from 0 mV to 10 mV of additional hysteresis in the comparator input stages. Adjustments in the HYSTERESIS control voltage may help to improve noi immunity and overall performance in harsh environments.
The OVERFLOW INH pin of the AD9012 determines how the converter handles overrange inputs (AIN ≥ + V REF ). In the “enabled” state (floating at –5.2 V), the OVERFLOW INH output will be at logic HIGH and all other outputs will be at logic LOW for overrange inputs (return-to-zero operation). In the “inhibited” state (tied to ground), the OVERFLOW INH output will be at logic LOW for overrange inputs, and all other digital outputs will be at logic HIGH (nonreturn-to-zero operation).The AD9012 provides outstanding error rate performance. This is due to tight control of comparator offt matching and a fault tolerant decoding stage. Additional improvements in error rate are possible through the addition of hysteresis (e HYSTERESIS control pin). This level of performance is extremely important in fault nsitive applications, such as digital radio (QAM).Dramatic improvemen的确近义词
ts in comparator design and construction give the AD9012 excellent dynamic characteristics, namely SNR (signal-to-noi ratio). The 160 MHz input bandwidth and low error rate performance give the AD9012 an SNR of 47 dB with a 1.23 MHz input. High SNR performance is particularly impor-tant in broadcast video applications where signals may pass through the converter veral times before the processing is complete. Pul signature analysis, commonly performed in advanced radar receivers, is another area that is especially dependent on high quality dynamic performance.
LAYOUT SUGGESTIONS
Designs using the AD9012, such as all high speed devices, must follow a few basic layout rules to ensure optimum performance.Esntially, the guidelines are meant to avoid many of the problems associated with high speed designs. The first require-ment is for a substantial ground plane around and under the AD9012. Separate ground plane areas for the digital and analog components may be uful, but the parate grounds should be connected together at the AD9012 to avoid the effects of “ground loop” currents.
The cond area that requires an extra degree of attention involves the three reference inputs, +V REF , REF MID , and –V REF .The +V REF input and the –V REF input should both be driven from
a low impedance source (note that the +V REF input is typically tied to analog ground). A low drift amplifier should provide satisfactory results, even over an extended temperature range. Adjustments at the REF MID input may be uful in improv-ing the integral linearity by correcting any reference ladder skews.The reference inputs should be adequately decoupled to ground through 0.1 µF chip capacitors to limit the effects of system noi on conversion accuracy. The power supply pins must also be decoupled to ground to improve noi immunity; 0.1 µF and 0.01 µF chip capacitors should be very effective.
The analog input signal is brought into the AD9012 through two parate input pins. It is very important that the two input pins be driven symmetrically with equal length electrical connections. Otherwi, aperture delay errors may degrade converter performance at high frequencies.
F
TTL ENCODE INPUT金骏眉
Figure 5.Typical Application
