REV PrM 04/02
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Low Power, +2.3 V to +5.5 V, 50 MHz
Complete D DS
Preliminary T echnical D ata AD9834
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.Tel: 781/329-4700 Fax: 781/326-8703© Analog Devices, Inc., 2002
FEATURES
+2.3 V to +5.5 V Power Supply 50 MHz Speed
Low Jitter Clock Output
Sine Output/Triangular Output Serial Loading
Power-Down Option
Narrowband SFDR > 72 dB
20 mW Power Consumption at 3 V 20-Pin TSSOP
APPLICATIONS Test Equipment
Slow Sweep Generator DDS Tuning
Digital Modulation
GENERAL DESCRIPTION
The AD9834 is a numerically controlled oscillator employing a pha accumulator, a SIN ROM and a 10-bit D/A converter integrated on a single CMOS chip. Clock rates up to 50 MHz are supported with a power supply from 2.3 V to 5.5 V.
FUNCTIONAL BLOCK DIAGRAM
BIT OUT
SCLK SDATA
小班户外活动目标
FSYNC SLEEP
PSELECT
MCLK
FSELECT
RESET
Capability for pha modulation and frequency modula-tion is provided. Frequency accuracy can be controlled to
one part in 0.25 billion. Modulation is effected by loading registers through the rial interface.
The AD9834 offers the ur a variety of output
waveforms. The SIN ROM can be bypasd so that a linear up/down ramp is output from the DAC. If the SIN ROM is not by-pasd, a sinusoidal output is available.Also, if a clock output is required, the MSB of the DAC data can be output, or the on-chip comparator can be ud.
The digital ction is driven by an on-board regulator which steps down the applied DVDD to +2.5 V when DVDD exceeds +2.5 V. The analog and digital ctions are independent and can be run from different power
AVDD can equals 5 V with DVDD equal to 3 V, etc.
The AD9834 has a power-down pin (SLEEP) which
allows external control of a power-down mode. Sections of the device which are not being ud can be powered down to minimi the current the DAC can be powered down when a clock output is being generated.The part is available in a 20-pin TSSOP package.
AD9834
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PRELIMINARY TECHNICAL DATA
Parameter
Min
Typ
Max Units
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS Resolution
10
过年禁忌
Bits Update Rate (f MAX )50MSPS I OUT Full Scale
呵斥
2.8mA Output Compliance 20.8
V DC Accuracy:
Integral Nonlinearity ±1LSB Differential Nonlinearity
±0.5
LSB
DDS SPECIFICATIONS Dynamic Specifications:Signal to Noi Ratio 50
dB f MCLK = 50 MHz, f OUT = f MCLK /4096Total Harmonic Distortion
-53
dBc f MCLK = 50 MHz, f OUT = f MCLK /4096Spurious Free Dynamic Range (SFDR):Wideband (0 to Nyquist)50dBc f MCLK = 50 MHz, f OUT = f MCLK /7NarrowBand (± 200 kHz)72
dBc f MCLK = 50 MHz, f OUT = f MCLK /7
Clock Feedthrough –55dBc Wake Up Time
1
ms COMPARATOR
Input Voltage Range 1
V p-p ac-coupled internally
Input Capacitance
10pF Input HighPass Cutoff Frequency 4MHz Input DC Resistance 1
M ΩInput DC Current 10
µA OUTPUT BUFFER Output Ri/Fall Time 20ns Using a 15 pF Load
Output Jitter
100ps rms When DAC data MSB is output VOLTAGE REFERENCE Internal Reference
1.116
1.2 1.284
V 1.2 V ± 7%
REFOUT Input Impedance 31K ΩReference TC
100
ppm/°C LOGIC INPUTS
V INH , Input High Voltage
D VDD –0.9V +3.6 V to +5.5 V Power Supply D VDD - 0.5V +2.7 V to +3.6 V Power Supply 2
V +2.3 V to + 2.7 V Power Supply V INL , Input Low Voltage 0.9V +3.6 V to +5.5 V Power Supply 0.5V +2.3 V to + 3.6 V Power Supply
I INH , Input Current 1µA C IN , Input Capacitance 10
pF POWER SUPPLIES f MCLK = 50 MHz, f OUT = f MCLK /7
海鲫鱼怎么做好吃AVDD 2.3 5.5V DVDD 2.3
5.5V I AA 45mA I DD 4
聚财型发财树
0.5 + 0.04/MHz mA I AA + I DD 4
710mA 3 V Power Supply 1015
mA 5 V Power Supply七夕图片
Low Power Sleep Mode 4
0.25
mA
干煸蚕蛹
DAC and Internal Clock Powered Down
NOTES 1
Operating temperature range is as follows: B Version: –40°C to +85°C; typical specifications are at 25؇C 2
Guaranteed by Design.3
Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.4
Measured with the digital inputs static and equal to 0 V or DVDD.
Specifications subject to change without notice. There is 95% test coverage of the digital circuitry.
SPECIFICATIONS
1
(V DD = +2.3 V to +5.5 V; AGND = DGND = 0 V; T A = T MIN to T MAX ; R SET = 6.8k Ω;
R LOAD = 200 Ω for IOUT and IOUTB unless otherwi noted)
AD9834
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TIMING C HARACTERISTICS 1
(V DD = +2.3 V to +5.5 V; AGND = DGND = 0 V, unless otherwi noted)
Parameter Limit at T MIN to T MAX Units Test Conditions/Comments
t 120ns min MCLK Period
t 28ns min MCLK High Duration t 38ns min MCLK Low Duration t 425ns min SCLK Period
t 510ns min SCLK High Duration t 610ns min SCLK Low Duration
t 75ns min FSYNC to SCLK Falling Edge Setup Time t 810ns min FSYNC to SCLK Hold Time
t 4 - 5ns max t 95ns min Data Setup Time t 103ns min Data Hold Time
t 118ns min FSELECT, PSELECT Setup Time Before MCLK Rising Edge t 11A *
8
ns min
FSELECT, PSELECT Setup Time After MCLK Rising Edge
1
Guaranteed by design, not production tested.*See Pin Description Section.
Figure 3.Control Timing
Figure 2.Master Clock
Figure 4.Serial Timing
Figure 1.Test Circuit With which Specifications are tested.
20pF
MCLK
SCLK
FSYNC
SDATA
AD9834
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PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS*
(T A = +25°C unless otherwi noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V DVDD to DGND . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V AVDD to DVDD . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V AGND to DGND. . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V CAP/2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.75 V Digital I/O Voltage to DGND –0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND –0.3 V to AVDD + 0.3 V Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . .–40°C to +85°C
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9834BRU –40°C to +85°C 20-Pin TSSOP (Thin Shrink Small Outline Package )RU-20EVAL-AD9834EB Evaluation Board
PIN CONFIGURATION
Storage Temperature Range . . . . . . . . .–65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . .+150°C TSSOP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . .143°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . .45°C/W Lead Temperature, Soldering (10 c) . . . . . . . . .300°C IR Reflow, Peak
Temperature . . . . . . . . . . . . . . .220°C
*Stress above tho listed under “Absolute Maximum Ratings” may cau permanent damage to the device. This is a stress rating only and functional operation of the device at the or any other conditions above tho listed in the operational ctions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) nsitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.Although the AD9834 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
FS MCLK IOUTB IOUT AGND VIN
SIGNBITOUT FSYNC SCLK SDATA SLEEP RESET
AD9834
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PIN FUNCTIONS DESCRIPTIONS
Pin #Mnemonic Function
ANALOG SIGNAL AND REFERENCE
1FS ADJUST Full-Scale Adjust Control. A resistor (R SET ) is connected between this pin and AGND. This
determines the magnitude of the full-scale DAC current. The relationship between R SET and the full-scale current is as follows:
IOUT FULL-SCALE = 18 x V REFOUT /R SET
V REFOUT = 1.20 V nominal , R SET = 6.8 k Ω typical
2REFOUT Voltage Reference Output. The AD9834 has an internal 1.20 V reference, which is made
available at this pin.
3COMP A DAC Bias Pin. This pin is ud for de-coupling the DAC bias voltage.17VIN Input to comparator. The comparator can be ud to generate a square wave from the
sinusoidal DAC output. The DAC output should be filtered appropriately before being applied to the comparator to improve jitter. When bits OPBITEN and SIGNPIB in the control register are t to 1, the comparator input is connected to VIN.
19,20IOUT, IOUTB Current Output. This is a high impedance current source. A load resistor of nominally 200 Ω
should be connected between IOUT and AGND. IOUTB should preferably be tied through an external load resistor of 200 Ω to AGND but can be tied directly to AGND. A 20pF capacitor to AGND is also recommended to prevent clock feedthrough.
POWER SUPPLY 4AVDD Positive power supply for the analog ction. AVDD can have a value from +2.3 V to +5.5 V.
A 0.1 µF decoupling capacitor should be connected between AVDD and AGND.
5DVDD Positive power supply for the digital ction. DVDD can have a value from +2.3 V to +5.5 V.
A 0.1 µF decoupling capacitor should be connected between DVDD and DGND.
6CAP/2.5V The digital circuitry operates from a +2.5 V power supply. This +2.5 V is generated from
DVDD using an on board regulator (when DVDD exceeds +2.7 V). The regulator requires a decoupling capacitor of typically 100 nF which is connected from CAP/2.5V to DGND. If DVDD is equal to or less than +2.7 V, CAP/2.5 V should be shorted to DVDD.
7DGND Digital Ground.18AGND Analog Ground.DIGITAL INTERFACE AND CONTROL 8MCLK Digital Clock Input. DDS output frequencies are expresd as a binary fraction of the
frequency of MCLK. The output frequency accuracy and pha noi are determined by this clock.
9FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is
ud in the pha accumulator. The frequency register to be ud can be lected using the pin FSELECT or the bit FSEL. When the bit FSEL is being ud to lect the frequency register,this pin, FSELECT, should be tied to CMOS high or low.
10PSELECT Pha Select Input. PSELECT controls which pha register, PHASE0 or PHASE1, is added
to the pha accumulator output. The pha register to be ud can be lected using the pin PSELECT or the bit PSEL. When the pha registers are being controlled by the bit PSEL,this pin, PSELECT, should be tied to CMOS high or low.
11RESET Active high digital input. RESET rets appropriate internal registers to zero which
corresponds to an analog output of midscale. RESET does not affect any of the addressable registers.
12SLEEP Active high digital input. When this pin is high, the DAC is powered down. This pin has the
same function as control bit SLEEP12.
13SDATA Serial Data Input. The 16-bit rial data word is applied to this input.14SCLK Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge.15FSYNC Active Low Control Input. This is the frame synchronisation signal for the input data. When
FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device.
16SIGN BIT OUT Logic Output. The comparator output is available on this pin or, alternatively, the MSB from
the NCO can be output on this pin. Setting bit OPBITEN in the control register to 1 enables this output pin. Bit SIGNPIB determines whether the comparator output or the MSB from the NCO is output on the pin.
AD9834
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PRELIMINARY TECHNICAL DATA Typical Performance Characteristics
怎么用酵母发面TPC 1. Typical Current Consumption vs. MCLK Frequency
TPC 4. Wide Band SFDR vs. f OUT/f MCLK for Various MCLK Frequencies TPC 7. Wake-Up Time vs.
Temperature TPC 2. Narrow Band SFDR vs. MCLK
Frequency
TPC 5. SNR vs. MCLK Frequency
TPC 8. V REFOUT vs. Temperature
TPC 3. Wide Band SFDR vs. MCLK
Frequency
TPC 6. SNR vs. f OUT/f MCLK for
Various MCLK Frequencies
