外文翻译
英文原文：
STM32 Microcontroller
Introduction
Requirements bad STM32 family is designed for high-performance, low-cost, low-power embedded applications designed specifically for ARM Cortex-M3 core. According to the performance into two different ries: STM32F103 "Enhanced" ries and STM32F101 "Basic" ries. Enhanced Series clock frequency of 72MHz, the highest performance of similar products product; basic clock frequency of 36MHz, 16-bit product prices get more than 16 products significantly enhance the performance and is 16 product urs the best choice. Both ries have built-in 32K to 128K of flash memory, the difference is the maximum capacity of the SRAM and peripheral combinations. At 72MHz, executing from Flash, STM32 power consumption 36mA, are 32 products on the market's lowest power, the equivalent of 0.5mA/MHz.
STM32F103 Performance Characteristics
1) Kernel. ARM32 bit CPU, the maximum operating frequency of 72MHz,
1.25DMIPS/MHz. Single-cycle multiply and hardware divide.
2) Memory. Integrated on-chip 32-512KB of Flash memory. 6-64KB SRAM
memory.
3) Clock, ret, and power management. 2.0-3.6V power supply and I / O interface, the drive voltage. POR, PDR and programmable voltage detector. 4-16MHz crystal. Embedded factory tuned 8MHz RC oscillator circuit. 40 kHz internal RC oscillator circuit. CPU clock for the PLL. With calibration for the RTC 32kHz crystal.
4) Low power consumption. Three kinds of low-power mode. Sleep, stop, standby mode. For RTC and backup registers supply VBAT.
5) Debug mode. Serial debugging and JTAG interface.
6) Direct data storage. 12-channel direct data storage controller. Supported peripherals: timers, ADC, DAC, SPI, IIC and USART.
7) Up to a maximum of 112 fast I / O ports. Depending on the model, there are 26,37,51,80, and 112 I / O ports, all ports can be mapped to 16 external interrupt
vectors. In addition to the analog input, all of them can accept the input of 5V or less.
8) Up to a maximum of 11 timers. Four 16-bit timers, each with 4 IC / OC / PWM or pul counter. 2 16 6-channel advanced control timer: up to 6 channels can be ud for PWM output. 2 watchdog timer. Systick timer: 24 down counter. Two 16-bit basic timer for driving DAC.
9) Up to a maximum of 13 communication interfaces. 2 IIC interface. 5 USART interfaces. 3 SPI interface, two and IIS reu. CAN interface. USB 2.0 full-speed interface. SDIO interface.
System Function
1) Integration of embedded Flash and SRAM memory ARM Cortex-M3 core. And 8/16 equipment compared, ARM Cortex-M3 32-bit RISC processor provides a higher code efficiency. STM32F103xx microcontrollers with an embedded ARM core, so it can be compatible with all ARM tools and software.
2) Embedded Flash memory and RAM memory. Built up to 512KB embedded Flash, can be ud to
store programs and data. Up to 64KB of embedded SRAM clock speed of the CPU can read and write.
3) Variable static memory. Variable static memory with 4 chip lects, supports four modes: Flash, RAM, PSRAM, NOR and NAND. After three FSMC interrupt lines connected to the OR after the nested vector interrupt controller. No read / write FIFO, except PCCARD, the code is executed from external memory is not supported Boot, the target frequency is equal to SYSCLK / 2, so the time when the system clock is 72MHz, 36MHz conducted in accordance with external access.
4) Nested Vectored Interrupt Controller. Can handle 43 maskable interrupt channels, providing 16 interrupt priority levels. Tightly coupled nested vectored interrupt controller to achieve lower latency interrupt handling directly pasd to the kernel interrupt vector table entry address, tightly coupled nested vectored interrupt controller kernel interface, allowing early treatment interruption, the latter to be more high-priority interrupt processing, support tail chain, auto-save processor state terrupts automatically restored on interrupt exit, no instructions intervention.
5) External interrupt / event controller. External interrupt / event controller consists for 19 to generate interrupt / event requests edge detector lines. Each line can be individually configured to lect the tr
igger event, it can be individually masked. There is a pending interrupt request registers to maintain state. When an external line appear longer than the internal APB2 clock-cycle pul, the external interrupt / event
controller is able to detect. Up to 112 GPIO connected to the 16 external interrupt lines.
6) Clocks and startup. At boot time or to the system clock lection, but the ret when the internal 8MHz crystal oscillator is lected as the CPU clock. Can choo a 4-16MHz external clock, and will be monitored to determine the success. During this time, the interrupt controller is disabled and the software management is subquently disabled. Also, if there is a need, PLL clock interrupt management fully available. Comparator can be ud more pre-configuration of the AHB frequency, including high-speed and low-speed APB APB, APB highest frequency of high-speed 72MHz, low-speed APB highest frequency of 36MHz.
Architectural Advantages
In addition to the new features Enhanced peripheral interfaces, STM32 ries also interconnect with other STM32 microcontrollers offer the same standard interface, such sharing of peripherals to enhance the entire product family, application flexibility, so that developers can a plurality of design r
eu the same software. New STM32 standard peripherals include 10 timers, two 12-bit ADC, two 12-bit DAC, two I2C interfaces, five USART interfaces and three SPI ports. There are 12 new products peripherals direct data storage channel, there is a CRC calculation unit, like other STM32 microcontrollers, the supports 96 unique identifier.
New ries also has followed the STM32 microcontroller family of products low voltage and energy saving are two advantages. 2.0V to 3.6V operating voltage range compatible with the mainstream of battery technologies such as lithium batteries and nickel-metal hydride batteries, the package also features a battery operation mode dedicated pin Vbat. 72MHz frequency to execute code from flash consumes only 27mA current. There are four low-power mode, the current consumption can be reduced to two microamps. Quick Start from low power mode to save energy too; starting circuit using STM32 internally generated 8MHz signal, the microcontroller from stop mode when you wake up with less than 6 microconds.
中文翻译：
单片机STM32
1 STM32的介绍
STM32系列基于专为要求高性能、低成本、低功耗的嵌入式应用专门设计的ARM Cortex-M3内核。按性能分成两个不同的系列：STM32F103“增强型”系列和STM32F101“基本型”系列。增强型系列时钟频率达到72MHz ，是同类产品中性能最高的产品；基本型时钟频率为36MHz ，以16位产品的价格得到比16位产品大幅提升的性能，是16位产品用户的最佳选择。两个系列都内置32K 到128K 的闪存，不同的是SRAM 的最大容量和外设接口的组合。时钟频率72MHz 时，从闪存执行代码，STM32功耗36mA ，是32位市场上功耗最低的产品，相当于0.5mA/MHz 。
2 STM32F103性能特点性能特点
1) 内核。ARM32位CPU ，最高工作频率72MHz ，1.25DMIPS/MHz 。单周期乘法和硬件除法。期乘法和硬件除法。
2) 存储器。片上集成32-512KB 的Flash 存储器。6-64KB 的SRAM 存储器。 3) 时钟、复位和电源管理。2.0-3.6V 的电源供电和I/O 接口的驱动电压。POR 、PDR 和可编程的电压探测器。4-16MHz 的晶振。内嵌出厂前调校的8MHz RC 振荡电路。内部40 kHz 的RC 振荡电路。用于CPU 时钟的PLL 。带校准用于RTC 的32kHz 的晶振。的晶振。
4) 低功耗。3种低功耗模式：休眠，停止，待机模式。为RTC 和备份寄存器供电的VBAT 。
5) 调试模式。串行调试和JTAG 接口。接口。
6) 直接数据存储。12通道直接数据存储控制器。支持的外设：定时器，ADC ，DAC ，SPI ，IIC 和USART 。
7) 最多高达112个的快速I/O 端口。根据型号的不同，有26，37，51，80，和112的I/O 端口，所有的端口都可以映射到16个外部中断向量。除了模拟输
入，所有的都可以接受5V 以内的输入。以内的输入。
8) 最多多达11个定时器。4个16位定时器，每个定时器有4个IC/OC/PWM
或者脉冲计数器。2个16位的6通道高级控制定时器：最多6个通道可用于PWM
输出。2个看门狗定时器。Systick 定时器：24位倒计数器。2个16位基本定时器用于驱动DAC 。
9) 最多多达13个通信接口。2个IIC 接口。5个USART 接口。3个SPI 接口，两个和IIS 复用。CAN 接口。USB 2.0全速接口。SDIO 接口。接口。
3 3 系统作用系统作用
1) 集成嵌入式Flash 和SRAM 存储器的ARM Cortex-M3内核。和8/16位设备相比，ARM Cortex-M3 3
2位RISC 处理器提供了更高的代码效率。STM32F103xx 微控制器带有一个嵌入式的ARM 核，所以可以兼容所有的ARM 工具和软件。工具和软件。
2) 嵌入式Flash 存储器和RAM 存储器。内置多达512KB 的嵌入式Flash ，可用于存储程序和数据。多达64KB 的嵌入式SRAM 可以以CPU 的时钟速度进行读写。行读写。
3) 可变静态存储器。可变静态存储器带有4个片选，支持四种模式：Flash ，RAM ，PSRAM ，NOR 和NAND 。3个FSMC 中断线经过OR 后连接到嵌套矢量中断控制器。没有读/写FIFO ，除PCCARD 之外，代码都是从外部存储器执行，不支持Boot ，目标频率等于SYSCLK/2，所以当系统时钟是72MHz 时，外部访问按照36MHz 进行。进行。
4) 嵌套矢量中断控制器。可以处理43个可屏蔽中断通道，提供16个中断优先级。紧密耦合的嵌套矢量中断控制器实现了更低的中断处理延迟，直接向内核传递中断入口向量表地址，紧密耦合的嵌套矢量中断控制器内核接口，允许中断提前处理，断提前处理，对后到的更高优先级的中断进行处理，对后到的更高优先级的中断进行处理，对后到的更高优先级的中断进行处理，支持尾链，支持尾链，支持尾链，自动保存处理器自动保存处理器状态，中断入口在中断退出时自动恢复，不需要指令干预。状态，中断入口在中断退出时自动恢复，不需要指令干预。
5) 外部中断/事件控制器。外部中断/事件控制器由用于19条产生中断/事件请求的边沿探测器线组成。
每条线可以被单独配置用于选择触发事件，也可以被
