Charge-Trap NAND Flash Memory
Charge Trap NAND Flash Memory Souvik Mahapatra p
E E Dept, IIT Bombay, India
C t ib ti S d C P Si h S G t K hitij A l k Contributions:Sandya C, Pawan Singh, Suyog Gupta, Kshitij Auluck, Piyush Dak, Sandeep Kasliwal, Udayan Ganguly, Dipankar Saha, Gautam Mukhopadhyay, Juzer Vasi
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Support:Applied Materials, Intel Corporation, SRC/GRC
Outline
FG NAND Flash scaling challenges
SiN bad charge trap flash –material dependence
P/E simulation of SiN Flash
Metal nanodot Flash
Scalability simulation of m-ND Flash
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NAND Flash Background
BL
DSL
CG
CD 15nm e l l s
WL CD 15nm
FG 50nm N o . o f c Figure: Samsung
SSL
TO 9nm
L=35nm
Memory state
SL
•Electron transfer between substrate & FG define memory state (write &era)state (write & era)
•FG surrounded by TO & CD acts as electron storage well (non-volatility, need 10yrs), though leak out occurs over time (retention loss )
3•Repeated Write/Era (10-100K needed) caus memory wear out (cycling endurance )
NAND Flash Scaling
•More memory, faster access, reduced cost •Guideline (ITRS roadmap):L=35nm (2009)CG
CD 15nm Guideline (ITRS roadmap): L=35nm (2009), 28nm (2010/11), 22nm (2013/14)…
SLC (1bit/ll)MLC (23bit /ll)f hi h TO 9nm
FG 50nm •SLC (1bit/cell), MLC (2 or 3 bits/cell) for higher density, higher reliability issues
L=35nm
Scaling penalty:
(1) Loss of CG –FG coupling (2)C ll t ll t lk
Solution: Discrete trap-bad charge storage
(2) Cell to cell cross talk (3) Non-scaling of TO, FG and CD thickness CG
CD,12nm CD thickness
(4) Non-scaling of operating voltage
TO, 6nm
CD, 12nm SiN, 6nm 4
(5) Higher reliability concern
Planer CTF
Devices & test chip demonstrated (Samsung)
•Memory window
Memory window
clo down with W/E
cycling
•Data keeps leaking
out(wor than FG!)
out (wor than FG!)
•Loss of memory
ti
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operation
CTF reliability wor than FG, no product yet
