Application Report
SPRAAR7A–January2013
USB2.0Board Design and Layout Guidelines DSPS Applications
ABSTRACT
This application report discuss schematic guidelines when designing a universal rial bus(USB) system.
Contents
1Background (1)
2USB PHY Layout Guide (2)
3Electrostatic Discharge(ESD) (8)
4References (10)
List of Figures
1Suggested Array Capacitors and a Ferrite Bead to Minimize EMI (2)
2Four-Layer Board Stack-Up (3)
3USB Connector (4)
43W Spacing Rule (4)
5Power Supply and Clock Connection to the USB PHY (5)
6USB PHY Connector and Cable Connector (6)
7Do Not Cross Plane Boundaries (7)
8Do Not Overlap Planes (7)
9Do Not Violate Image Planes (8)
List of Tables
1Background
Clock frequencies generate the main source of energy in a USB design.The USB differential DP/DM pairs operate in high-speed mode at480Mbps.System clocks can operate at12MHz,48MHz,and60MHz.
The USB cable can behave as a monopole antenna;take care to prevent RF currents from coupling onto the cable.
When designing a USB board,the signals of most interest are:
•Device interface signals:Clocks and other signal/data lines that run between devices on the PCB.
•Power going into and out of the cable:The USB connector socket pin1(VBUS)may be heavily filtered and need only pass low frequency signals of less than~100KHz.The USB socket pin4
(analog ground)must be able to return the current during data transmission,and must be filtered
sparingly.
•Differential twisted pair signals going out on cable,DP and DM:Depending upon the data transfer rate, the device terminals can have signals with fundamental frequencies of240MHz(high speed),6
MHz(full speed),and750kHz(low speed).
•External crystal circuit(device terminals XI and X0):12MHz,19.2MHz,24MHz,and48MHz fundamental.When using an external crystal as a reference clock,a24MHz and higher crystal is
highly recommended.
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USB PHY Layout Guide 2USB PHY Layout Guide
The following ctions describe in detail the specific guidelines for USB PHY Layout.
2.1General Routing and Placement
U the following routing and placement guidelines when laying out a new design for the USB physical layer(PHY).The guidelines help minimize signal quality and electromagnetic interference(EMI)
problems on a four-or-more layer evaluation module(EVM).
•Place the USB PHY and major components on the un-routed board first.For more details,e Section2.2.3.
•Route the high-speed clock and high-speed USB differential signals with minimum trace lengths.
•Route the high-speed USB signals on the plane clost to the ground plane,whenever possible.
•Route the high-speed USB signals using a minimum of vias and corners.This reduces signal reflections and impedance changes.
•When it becomes necessary to turn90°,u two45°turns or an arc instead of making a single90°turn.This reduces reflections on the signal traces by minimizing impedance discontinuities.
•Do not route USB traces under or near crystals,oscillators,clock signal generators,switching regulators,mounting holes,magnetic devices or IC’s that u or duplicate clock signals.
•Avoid stubs on the high-speed USB signals becau they cau signal reflections.If a stub is unavoidable,then the stub should be less than200mils.
•Route all high-speed USB signal traces over continuous planes(V
CC or GND),with no interruptions.
Avoid crossing over anti-etch,commonly found with plane splits.
2.2Specific Guidelines for USB PHY Layout
The following ctions describe in detail the specific guidelines for USB PHY Layout.
2.2.1Analog,PLL,and Digital Power Supply Filtering
To minimize EMI emissions,add decoupling capacitors with a ferrite bead at power supply terminals for the analog,pha-locked loop(PLL),and digital portions of the chip.Place this array as clo to the chip as possible to minimize the inductance of the line and noi contributions to the system.An analog and digital supply example is shown in Figure1.In ca of multiple power supply pins with the same function, tie them up to a single low-impedance point in the board and then add the decoupling capacitors,in
addition to the ferrite bead.This array of caps and ferrite bead improve EMI and jitter performance.Take both EMI and jitter into account before altering the configuration.
Figure1.Suggested Array Capacitors and a Ferrite Bead to Minimize EMI
2USB2.0Board Design and Layout Guidelines SPRAAR7A–January2013
Signal 1
USB PHY Layout Guide
Consider the recommendations listed below to achieve proper ESD/EMI performance:
•U a 0.01μF cap on each cable power VBUS line to chassis GND clo to the USB connector pin.•U a 0.01μF cap on each cable ground line to chassis GND next to the USB connector pin.
•If voltage regulators are ud,place a 0.01μF cap on both input and output.This is to increa the
immunity to ESD and reduce EMI.For other requirements,e the device-specific datasheet.
2.2.2Analog,Digital,and PLL Partitioning
If parate power planes are ud,they must be tied together at one point through a low-impedance bridge or preferably through a ferrite bead.Care must be taken to capacitively decouple each power rail clo to the device.The analog ground,digital ground,and PLL ground must be tied together to the low-impedance circuit board ground plane.
2.2.3Board Stackup
Becau of the high frequencies associated with the USB,a printed circuit board with at least four layers is recommended;two signal layers parated by a ground and power layer as shown in Figure 2.
Figure 2.Four-Layer Board Stack-Up
The majority of signal traces should run on a single layer,preferably SIGNAL1.Immediately next to thi
s layer should be the GND plane,which is solid with no cuts.Avoid running signal traces across a split in the ground or power plane.When running across split planes is unavoidable,sufficient decoupling must be ud.Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.
2.2.4Cable Connector Socket
Short the cable connector sockets directly to a small chassis ground plane (GND strap )that exists
immediately underneath the connector sockets.This shorts EMI (and ESD)directly to the chassis ground before it gets onto the USB cable.This etch plane should be as large as possible,but all the conductors coming off connector pins 1through 6must have the board signal GND plane run under.If needed,scoop out the chassis GND strap etch to allow for the signal ground to extend under the connector pins.Note that the etches coming from pins 1and 4(VBUS power and GND)should be wide and via-ed to their
respective planes as soon as possible,respecting the filtering that may be in place between the connector pin and the plane.See Figure 3for a schematic example.
Place a ferrite in ries with the cable shield pins near the USB connector socket to keep EMI from getting onto the cable shield.The ferrite bead between the cable shield and ground may be valued between 10Ωand 50Ωat 100MHz;it should be resistive to approximately 1GHz.To keep EMI from getting onto the cable bus power wire (a very large antenna)a ferrite may be placed in ries with cable bus power,
VBUS,near the USB connector pin 1.The ferrite bead between connector pin 1and bus power may be valued between 47Ωand approximately 1000Ωat 100MHz.It should continue being resistive out to approximately 1GHz,as shown in Figure 3.
USB PHY Layout Guide
Figure3.USB Connector
2.2.5Clock Routings
To address the system clock emissions between devices,place a~10to130Ωresistor in ries with the clock signal.U a trial and error method of looking at the shape of the clock waveform on a high-speed oscilloscope and of tuning the value of the resistance to minimize waveform distortion.The value on this resistor should be as small as possible to get the desired effect.Place the resistor clo to the device
generating the clock signal.If an external crystal is ud,follow the guidelines detailed in the Selection and Specification of Crystals for Texas Instruments USB2.0Devices(SLLA122).
When routing the clock traces from one device to another,try to u the3W spacing rule.The distance from the center of the clock trace to the center of any adjacent signal trace should be at least three times the width of the clock trace.Many clocks,including slow frequency clocks,can have fast ri and fall
times.Using the3W rule cuts down on crosstalk between traces.In general,leave space between eac
h of the traces running parallel between the devices.Avoid using right angles when routing traces to minimize the routing distance and impedance discontinuities.For further protection from crosstalk,run guard traces beside the clock signals(GND pin to GND pin),if possible.This lesns clock signal coupling,as shown in Figure4.
Figure4.3W Spacing Rule
4USB2.0Board Design and Layout Guidelines SPRAAR7A–January2013
USB PHY Layout Guide 2.2.6Crystals/Oscillator
Keep the crystal and its load capacitors clo to the USB PHY pins,XI and XO(e Figure5).Note that frequencies from power sources or large capacitors can cau modulations within the clock and
should not be placed near the crystal.In the instances,errors such as dropped packets occur.A placeholder for a resistor,in parallel with the crystal,can be incorporated in the design to assist oscillator startup.
Power is proportional to the current squared.The current is I=C*dv/dt,since dv/dt is a function of the
PHY,current is proportional to the capacitive load.Cutting the load to1/2decreas the current by1/2 and the power to1/4of the original value.For more details on crystal lection,e the Selection and
Specification of Crystals for Texas Instruments USB2.0Devices(SLLA122).
USB PHY
Figure5.Power Supply and Clock Connection to the USB PHY
2.2.7DP/DM Trace
Place the USB PHY as clo as possible to the USB2.0connector.The signal swing during high-speed operation on the DP/DM lines is relatively small(400mV±10%),so any differential noi picked up on the twisted pair can affect the received signal.When the DP/DM traces do not have any shielding,the
traces tend to behave like an antenna and picks up noi generated by the surrounding components in the environment.To minimize the effect of this behavior:
•DP/DM traces should always be matched lengths and must be no more than4inches in length;
otherwi,the eye opening may be degraded(e Figure6).
•Route DP/DM traces clo together for noi rejection on differential signals,parallel to each other and within two mils in length of each other(start the measurement at the chip package boundary,not to the balls or pins).
•A high-speed USB connection is made through a shielded,twisted pair cable with a differential characteristic impedance of90Ω±15%.In layout,the impedance of DP and DM should each be45Ω
±10%.
•DP/DM traces should not have any extra components to maintain signal integrity.For example,traces cannot be routed to two USB connectors.
