专利名称：INVALID PROCESSING SYSTEM FOR CACHE MEMORY
发明人：NAKAYAMA KAZUTO
申请号：JP27498389
申请日：19891024
公开号：JPH03137746A
公开日：
19910612
专利内容由知识产权出版社提供
摘要：PURPOSE:To eliminate a competitive control circuit in a cache memory by generating an invalid request when a write signal detection means provided in a two port memory detects a write signal from a system bus. CONSTITUTION:When an access request signal SBRQ from the system bus 13 to a memory 12 becomes active, the write signal SBWR becomes active also and the memory 12 actually starts a write operation, an invalid request signal INVRQ is outputted from an invalid processing control part 12a to the cache memory 11. The memory 11 decides whether an address given from the memory 12 is the one held in a tag part 30 or not. When it is concerned, an invalid processing is executed. When the processing terminates, an acknowledge signal ACK is outputted to the memory 12. When the memory 12 receives the signal ACK, it ts the signal SBWR active and simultaneously ts a signal IBVRQ inactive. Thus, a write processing from the bus 13 is terminated.
申请人：OKI ELECTRIC IND CO LTD
更多信息请下载全文后查看
