MEMORY存储芯片MCIMX281AVM4B中文规格书

Electrical characteristics

Table11. Operating单车怎么骑 Ranges (continued)

DDR I/O supplyNVCC_DRAMLPDDR21.141.21.3V—

DDR3L1.281.351.45V—

DDR31.431.51.575V—

NVCC_DRAM2P5—2.252.52.75V—

GPIO suppliesNVCC_CSI—1.651.8,3.6VAll digital I/O supplies

NVCC_ENET

NVCC_GPIO

NVCC_UART

NVCC_LCD

NVCC_NAND

NVCC_SD1

A/D converterVDDA_ADC_3P3—3.03.153.6VVDDA_ADC_3P3 must be

powered when chip is in RUN

mode, IDLE mode, or SUSPEND

mode.

VDDA_ADC_3P3 should not be

powered when chip is in SNVS

mode.

2.8,(NVCC_xxxx) must be powered

3.3(unless otherwi specified in this

data sheet) under normal

conditions whether the associated

I/O pins are in u or not.

Temperature Operating Ranges

Junction TjIndustrial-40—105

temperature

o

CSee the application note,

6Ultra中学语文教案 Lite Product Lifetime Usage

Estimates for information on

product lifetime (power-on years)

for this processor.

1

Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage t

point = (V + the supply tolerance). This result in an optimized power/speed ratio.

min

2

In tting VDD_HIGH_IN voltage, refer to the Errata ERR010690 (SNVS_LP Registers Ret Issue).

3

In tting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the 6UltraLite Hardware

Development Guide (IMX6ULHDG).

Table 12 shows on-chip LDO regulators that can supply on-chip loads.

Table12. On-Chip LDOs and their On-Chip Loads

1

Voltage SourceLoadComment

VDD_HIGH_CAPNVCC_DRAM_2P5Board-level connection to VDD_HIGH_CAP

1

On-chip LDOs are designed to supply 6UltraLite loads and must not be ud to supply external loads.

4.1.4External clock sources

Each 6UltraLite processor has two external input system clocks: a low frequency (RTC_XTALI) and

a high frequency (XTALI).

6UltraLite Applications Processors for Industrial Products, Rev. 2.2, 05/2017

24NXP Semiconductors

Electrical characteristics

The RTC_XTALI is ud for low-frequency functions. It supplies the clock for wake-up circuit,

power-down real time clock operation, and slow system and watch-dog counters. The clock input can be

connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is

an internal ring oscillator, which can be ud instead of the RTC_XTALI if accuracy is not important.

The system clock input XTALI is ud to generate the main system clock. It supplies the PLLs and other

peripherals. The system clock input can be connected to either external oscillator or a crystal using internal

oscillator amplifier.

Table 13 shows the interface frequency requirements.

Table13. External Input Clock Frequency

Parameter DescriptionSymbolMinTypMaxUnit

RTC_XTALI Oscillator—32.768/32.0—kHz

1,23

XTALI Oscillatorf—24—MHz

2,4

1

2

f

ckil

xtal

External oscillator or a crystal with internal oscillator amplifier.

The required frequency stability of this clock source is application dependent. For recommendations, e the Hardware

Development Guide for 6UltraLite Applications Processors (IMX6ULHDG).

3

Recommended nominal frequency 32.768kHz.

4

External oscillator or a fundamental frequency crystal with internal oscillator amplifier.

The typical values shown in Table 13 are required for u w公司员工绩效考核方案 ith NXP BSPs to ensure preci time keeping

and USB operation. For RTC_XTALI operation, two clock sources are available.

•On-chip 40 kHz ring osc即身成佛 illator—this clock source has the following characteristics:

—Approximately 25 A more Idd than crystal oscillator

—Approximately 50% tolerance

—No external component required

—Starts up quicker than 32 kHz crystal oscillator

•External crystal oscillator with on-chip support circuit:

—At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit

switches over to the crystal oscillator automatically.

—Higher accuracy than ring oscillator

—If no external crystal is prent, then the ring oscillator is utilized

The decision of choosing a clock source should be taken bad on real-time clock u and precision

ti葫芦怎么吃 me-out.

4.1.5Maximum supply currents

The data shown in Table 14 reprent a u ca designed specifically to show the maximum current

consumption possible. All cores are running at the defined maximum frequency and are limited to L1

cache access only to ensure no pipeline stalls. Although a valid condition, it would have a very limited

practical u ca, if at all, and be limited to an extremely low duty cycle unless the intention was to

spec一把刀顺水漂有眼睛没眉毛是什么 ifically show 布娃娃英语 the worst ca power consumption.

6UltraLite Applications Processors for Industrial Products, Rev. 2.2, 05/2017

NXP Semiconductors25