移位寄存器Port

移位寄存器Port(clk,load:in std_logic; din:in std_std_logic_vector(7downto 0);pb:out std_logic);

end Archi杭州居住证办理 tecture one of shfrt is begin process(clk,load) variable reg8 :std_logic_vector(7

downto 0); begin if clk’ event and clk=’1 then if load =’1’ then reg8::=din; el

reg8(6 downto 0):=reg8(7 downto 1); end if; end if ; qb<=reg8(0) end process; end one;

带异步清零全加器 entity adder4b is port(clr,cin:in std_logic; a,b孔子父亲 :in std_logic_vector(3

downto 0); s: out std_logic_vector(3 downto 0); cout: out std_logic)；end adder4b; architecture

art of adder4b is signal sint:std_logic_vector(4 downto 0); signal aa,bb:std_logic_vector(4

downto 0); begin process(clr)b begin if clr=’1’ then sint<=”00000”; el aa<=’0’&a;

bb<=’0’&b; sint <=aa+bb+cin； end if; s<=sint（3 downto 0）; cout<=sint(4); end process;

end art;

多位加，减法器entity jianfaqi is port(a,b:in std_logic_vector(0 to 3); c0:in std_logic;

c1:out std_logic; d:out std_logic_vector(0 to 3); end;

architecture a of jianfaqi begin process begin if a>b+c0 then b<=a-(b+c0); c1<=’0;

el c1<=’1’ d<=(“10000”)-(b+c0-a); end if; end p党章下载 rocess; end;

n位二进制计数器设计 entiy cnt4 is port(cik:in std_logic; q;out std_logic_vector(3

downto 0)； end cnt4; architecture behave of cnt4 is signal q1:std_logic_vector(3

downto 0); begin process(clk) begin if (clk’event and clk=’1’)then q1<=q1+1; end

if; end process; q<=q1: end behave;

32加法计数器

Port(clk,clr:in std-logic;dout0,dout1:out std-logic-vector(3 downto 0)); end; architecture art of

counter-plus is signal d0,d1:std-logic-vector(3 downto 0); begin process(clk,clr,) begin if

clr=’1’then d1 <=(others =>’0’);d0 <=”0000”; elsif clk’evet and clk=’1’t书籍 hen if(d1 =3 and d0

=1)then d1 <=”0000”; d0 <=”0000”; elsif(d0=1)then d0<=”0000”; d1<=d1+1; el

d0<=d0+1; end if; end if; dout 1 <=d1;dout0 <=d0; end process; end art;

8位并入/串出

Port(lir,clk,:in std-logic; din:in std-logic-vector(7 downto 0); dout;out-logic); end;

architecture art of shift-p is signal temp:陶渊明的田园诗 std-logic-vector(7 downto 0); begin process()

begin if clr=’0’then thmp <=(others=>’0’); elsif(clk’event and clk=’1’)then

if(load=’1’)then itemp<=din; elsif en =’1’then temp<=shl(temp,’1’); temp(0)<=’0’; end

if; end if; end process; dout<=temp(7); end art;

三态门 PORT( datain : IN STD_LOGIC; outen : IN STD_LOGIC; dataout :

OUT STD_LOGIC ); END tri_v; ARCHITECTURE a OF tri_v IS BEGIN

PROCESS (outen，datain) BEGIN IF outen = '0' THEN dataout<= 'Z'; ELSE

dataout<= datain ; END IF; END PROCESS; END a;

Jk触发器 PORT(j, k : IN STD_LOGIC; Clk : IN STD_LOGIC; q, qb : OUT

S离婚协议书格式 TD_LOGIC); END jkdff; ARCHITECTURE a OF jkdff IS SIGNAL

qtmp,qbtmp:STD_LOGIC BEGIN PROCESS(clk,j,k) BEGIN IF clk='1' AND

clk'event THEN IF j='0' AND k='0' THEN NULL; ELSIF j='0' AND k='1' THEN

qtmp<='0'; qbtmp<='1'; ELSIF j='1' AND k='0' THEN qtmp<='1'; qbtmp<='0';

ELSE qtmp<=NOT qtmp ；qbtmp<=NOT qbtmp; END IF; END IF;

q<=qtmp; qb<=qbtmp; END PROCESS; END a;