dq9

DDR内存条引脚定义图管脚定义图

DDR2SDRAMDIMM240pin

DDR:DoubleDataRate

DIMM:DualInlineMemoryModule

SDRAM:SynchronousDynamicRandomAccessMemory,SynchronoustoPositiveClock

Edge.

PINCONFIGURATIONS(Frontside/backside)

Front

n

ol

n

ol

n

ol

n

ol

n

12

1

12

2

12

3

12

4

5

6

12

7

12

8

12

9

13

0

13

1

13

2

13

3

ol

VSS

DQ4

DQ5

VSS

n

15

1

15

2

15

3

15

4

Back

ol

VSS

DQ28

DQ29

VSS

n

18

1

18

2

18

3

18

4

5

6

18

7

18

8

18

9

19

0

19

1

19

2

19

3

ol

VDDQ

A3

A1

VDD

CK0

CK0

#

VDD

A0

VDD

BA1

VDDQ

RAS

#

S0#

n

1

2

21

3

21

4

21

5

21

6

21

7

21

8

21

9

22

0

22

1

22

2

3

ol

QS14

S14

#

VSS

DQ46

DQ47

VSS

DQ52

DQ53

VSS

RFU

RFU

VSS

PiSymbPiSymbPiSymbPiSymbPiSymbPiSymbPiSymbPiSymb

21DM5/D

21NC/DQ

1

VREF

31

DQ19

61

A4

2

VSS

3

DQ0

4

DQ1

5

VSS

32

VSS

91

VSS

62

VDDQ

92

DQS5#

93

DQS5

94

VSS

95

DQ42

96

DQ43

97

VSS

98

DQ48

99

DQ49

VSS

SA2

NC

VSS

33

DQ24

63

A2

34

DQ25

64

VDD

35

VSS

65

VSS

12DM0/D15DM3/D18

QS9

S9

#

VSS

DQ6

DQ7

VSS

DQ12

DQ13

VSS

5

QS12

6

S12

#

15

7

15

8

15

9

16

0

16

1

16

2

16

3

VSS

DQ30

DQ31

VSS

CB4

CB5

VSS

12NC/DQ15NC/DQ18

6

DQS0

#

36

DQS3

#

66

VSS

7

DQS0

37

DQS3

67

VDD

8

VSS

9

DQ2

10

DQ3

11

VSS

12

DQ8

13

DQ9

14

VSS

38

VSS

68

PAR_I

N

39

DQ26

69

VDD

40

DQ27

70

41

VSS

42

CB0

43

CB1

44

VSS

A10/A10

P

0

10

1

10

2

10

3

71

BA0

72

VDDQ

73

WE#

22DM6/D

QS15

74

CAS

#

10DQS6

#

13DM1/D16DM8/D19VDDQ

22NC/DQ

4

15

DQS1

#

45

DQS8

#

75

VDDQ

16

DQS1

46

DQS8

76

S1

#

17

VSS

18

RESET

#

47

VSS

48

CB2

49

CB3

50

VSS

77

0DT1

78

VDDQ

79

VSS

80

DQ32

10

5

10

6

10

7

10

8

10

9

11

0

11

1

11

2

11

3

11

4

11

5

11

6

11

7

11

8

11

9

12

0

DQS6

VSS

DQ50

DQ51

VSS

DQ56

DQ57

VSS

DQS7

#

DQS7

VSS

DQ58

DQ59

VSS

SDA

SCL

4

5

13

6

13

7

13

8

13

9

14

0

14

1

14

2

14

3

14

4

14

5

6

7

14

8

14

9

15

0

QS10

S10

#

VSS

RFU

RFU

VSS

DQ14

DQ15

VSS

DQ20

DQ21

VSS

4

QS17

5

S17

#

16

6

16

7

16

8

16

9

17

0

17

1

17

2

17

3

17

4

17

5

6

7

17

8

17

9

18

0

VSS

CB6

CB7

V实习月报告 SS

VDDQ

CKE1

VDD

NC

NC

VDDQ

A12

A9

VDD

A8

A6

4

5

6

19

7

19

8

19

9

20

0

20

1

2

3

20

4

20

5

20

6

20

7

20

8

20

9

21

0

ODT0

4

22

5

6

22

7

22

8

22

9

23

0

23

1

2

3

23

4

23

5

23

6

23

7

8

23

9

24

0

S15

#

VSS

DQ54

DQ55

VSS

DQ60

DQ61

VSS

13NC/DQ16NC/DQ19

19NC/A122

3

VDD

VSS

DQ36

DQ37

VSS

19

NC

20

VSS

21

DQ10

51

VDDQ

81

DQ33

22

DQ11

52

CKE0

82

VSS

23

VSS

53

VDD

NC/BA

2

ERR_

OUT

83

DQS4

#

84

DQS4

85

VSS

20DM4/D23DM7/D

QS13

S13

#

VSS

DQ38

DQ39

VSS

DQ44

DQ45

VSS

QS16

S16

#

VSS

DQ62

DQ63

VSS

20NC/DQ23NC/DQ

24

DQ16

54行程安排模板

25

DQ17

55

26

VSS

56

VDDQ

86

DQ34

87

DQ35

88

VSS

89

DQ40

90

DQ41

14DM2/D17

QS11

S11

#

VSS

DQ22

DQ23

14NC/DQ17

27

DQS2

#

57

A11

28

DQS2

58

A7

29

VSS

59

VDD

23VDDS

PD

SA0

SA1

30

DQ18

60

A5

Note:Pin196isNCfor512MB,orA13for1GBand2GB;pin54isNCfor512MBand1

GB,orBA2for2GB.

PinDescriptions

Pinnumbersmaynotcorrelatewithsymbols;refertoPinAssignmenttableaboveformorein

formation.

PinNumbers

Symbol

Type

Description

On-DieTermination:ODT(registeredHIGH)en

ablesterminationresistanceinternaltotheDDR

abled,ODTisonlyapplie

195

ODT0

Inputdtoeachofthefollowingpins:DQ,DQS,DQ

S#,RDQS,RDQS#,CB,in

putwillbeignoredifdisabledviatheLOAD

MODEcommand.

Clock:CKandCK#aredifferentialclockinput

ressandcontrolinputsignalsaresam

185,186

CK0,CK0#Input

pledonthecrossingofthepositiveedgeofC

KandnegativeedgeofCK#.Outputdata(DQ

sandDQS/DQS#)isreferencedtothecrossing

sofCKandCK#.

ClockEnable:CKE(registeredHIGH)activates

andCKE(registeredLOW)deactivatesclockin

cific

circuitrythatinabled/disabledisdependent

ontheDDR2SDRAMconfigurationandoperat

providesPRECHARGEP

OWER-DOWNandSELFREFRESHoperations

(alldevicebanksidle),orACTIVEPOWERD

OWN(rowACTIVEinanydevicebank).CKE

issynchronousforPOWER-DOWNentry,PO

WER-DOWNexit,outputdisable,andforSEL

52

CKE0

synchronousforS

uffers(excludingC

K,CK#,CKE,andODT)大商人 aredisabledduringP

uffers(excludingCKE)

nSSTL_18inputbutwilldetectaLVCMOSL

OWlevelonceVDDisappliedduringfirstpo

refhasbecomestableduringth

epoweronandinitializationquence,itmust

bemaintainedforproperoperationoftheCKE

perlf-refreshoperationVRE

Fmustbemaintainedtothisinput.

ChipSelect:S#enables(registeredLOW)and

193

S0#

Inputdisables(registeredHIGH)thecommanddecode

mandsaremaskedwhenS#isregist

eredHIGH.S#providesforexternalranklect

iononsystemswithmultipleranks.S#isconsi

deredpartofthecommandcode.

73,74,192

RAS#,CAS

#,WE#

Input

CommandInputs:RAS#,CAS#,andWE#(alon

gwithS#)definethecommandbeingentered.

BankAddressInputs:BA0–BA1/BA2defineto

whichdevicebankanACTIVE,READ,WRIT

54(2GB),71,190

BA0,BA1,

BA2(2GB)

Input

E,orPRECHARGEcommandisbeingapplied.

BA0–BA1definewhichmoderegisterincludin

gMR,EMR,EMR(2),andEMR(3)isloadedd

uringtheLOADMODEcommand.

AddressInputs:ProvidetherowaddressforA

CTIVEcommands,andthecolumnaddressand

autoprechargebit(A10)forRead/Writecom

57,58,60,61,63,70公务员个人简历 ,176,177,1

79,180,182,183,188,196(1GB,

2GB)

A0–A12(512

MB)A0–A1

3(1GB,2GB)

mands,tolectonelocationoutofthememor

yarrayintherespectivebank.A10sampleddu

InputringaPRECHARGEcommanddetermineswhet

herthePRECHARGEappliesto喜爱 onedeviceba

nk(A10LOW,devicebanklectedbyBA0–B

A1/BA2)oralldevicebanks(A10HIGH).The

addressinputsalsoprovidetheop-codeduring

aLOADMODEcommand.

3,4,9,10,12,13,21,22,24,25,

30,31,33,34,39,40,80,81,8

6,87,89,90,95,96,98,99,107,

108,110,111,116,117,122,12

3,128,129,131,132,140,141,1DQ0–DQ63

43,144,149,150,152,153,158,

159,199,200,205,206,208,209,清明团子

214,215,217,218,226,227,22

9,230,235,236

DataStrobe:Outputwithreaddata,inputwith

ge-alignedwithreaddata,centeralignedwith

6,7,15,16,27,28,36,37,45,4DQS0–DQS8,

6,83,84,92,93,104,105,113,1DQS0#–D

14,126,135,147,156,165,203,

164,202,211,223,232

QS17#,DM0I/O

9–DQS17)

212,224,233125,134,146,155,

–DM8(DQS

#isonlyudwhendifferential

datastrobemodeinabledviatheLOADM

ataMask:DMisanin

ataism

askedwhenDMissampledHIGHalongwitht

ghDM

pinsareinput-only,theDMloadingisdesigned

I/O

DataInput/Output:Bidirectionaldatabus.

isdisab心理起源说 led,DQS0–DQS17becomeDM0–DM8

andDQS9#–DQS17#arenotud.

42,43,48,49,161,162,167,168CB0–CB7

6855

PAR_INERR_OUT

I/O

CheckBits.

InputParitybitfortheaddressandcontrolbus.

OutpParityerrorfoundontheaddressandcontrolbut

us.

SerialClockforPrence-Detect:SCLisudt

120SCLInputosynchronizetheprence-detectdatatransfert

oandfromthemodule.

101,239,240SA0–SA2Input

Prence-DetectAddressInputs:Thepinsare

udtoconfiguretheprence-detectdevice.

SerialPrence-DetectData:SDAisabidirectio

119SDAI/O

nalpinudtotransferaddressanddatainto

andoutoftheprence-detectportionofthemodule.

AsynchronouslyforcesallregisteredoutputsLO

18RESET#Input

WwhenRESET#gnalcanbe

udduringpoweruptoensurethatCKEisL

OWandDQsareHigh-Z.

53,59,64,67,69,172,178,184,

187,189,197,

51,56,62,72,75,78,170,175,1

81,191,194,1

2,5,8,11,14,17,20,23,烤鸭卷 26,29,

32,35,38,41,44,47,50,65,6

6,79,82,85,88,91,94,97,100,

103,106,109,112,115,118,121,

VDD

Suppl

y

Suppl

y

Supply

PowerSupply:1.8V0.1V.

VDDQDQPowerSupply:1.8V0.1V.

VREFSSTL_18referencevoltage.

124,127,130,133,136,139,142,VSS

145,148,151,154,157,160,16

3,166,169,198,201,204,207,2

10,213,216,219,222,225,228,

231,234,237238

19,54(512MB,1GB),76,77,102,

171,196(512MB),173,174,

137,138,220,221

VDDSPD

Supply

Ground.

SupplSerialEEPROMpositivepowersupply:+1.7Vt

y

—

—

o+3.6V.

NoConnect:Thepinsshouldbeleftunconnected.

Rervedforfutureu.

NCRFU