Shenzhen First-Rank Technology Co., Ltd
S P E C I F I C A T I O N
T24C02A/T24C04A/T24C08A/T24C16A
Version 1.1 rerves the right to change this documentation without prior notice.
▉Features
●Wide Voltage Operation
- VCC = 1.8V to 5.5V
●Operating Ambient Temperature: -40℃to +85℃
●Internally Organized:
- T24C02A, 256 X 8 (2K bits)
- T24C04A, 512 X 8 (4K bits)
- T24C08A, 1024 X 8 (8K bits)
- T24C16A, 2048 X 8 (16K bits)
●Two-wire Serial Interface
●Schmitt Trigger, Filtered Inputs for Noi Suppression
●Bidirectional Data Transfer Protocol
● 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
●Write Protect Pin for Hardware Data Protection
●8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes
●Partial Page Writes Allowed
●Self-timed Write Cycle (5 ms max)
●High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
●8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages
●Die Sales: Wafer Form, Waffle Pack
▉General Description
The T24C02A/T24C04A/T24C08A/T24C16A provides 2048/4096/8192/16384 bits of rial electrically erasable and programmable read-only memory (EEPROM) organized as
256/512/1024/2048 words of 8 bits each. The device is optimized for u in many industrial and commercial applications where low-power and low-voltage operations are esntial. The
T24C02A/T24C04A/T24C08A/T24C16A is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accesd via a two-wire rial interface.
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▉Pin Configuration
qq非主流签名▉Pin Descriptions
Table 1: Pin Configuration
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Pin Designation Type Name and Functions A0 - A2 I Address Inputs
SDA I/O & Open-drain Serial Data
SCL I Serial Clock Input
WP I Write Protect
GND P Ground
VCC P Power Supply
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▉Pin Descriptions
DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the T24C02A. Eight 2K devices may be addresd on a single bus system (device addressing is discusd in detail under the Device Addressing ction).
The T24C04A us the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addresd on a single bus system. The A0 pin is a no connect and can be connected to ground. The T24C08A only us the A2 input for hardwire addressing and a total of two 8K devices may be addresd on a single bus system. The A0 and A1 pins are no connects and can be connected to ground.
The T24C16A does not u the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects and can be connected to ground.
SERIAL DATA (SDA): The SDA pin is bi-directional for rial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL): The SCL input is ud to positive edge clock data into each EEPROM device and negative edge clock data out of each device.
WRITE PROTECT (WP): The T24C02A/T24C04A/T24C08A/T24C16A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following Table 2.
Table 2: Write Protect
Part of the Array Protected
WP Pin Status
T24C02A T24C04A T24C08A T24C16A At VCC Full (2K) Array Full (4K) Array Full (8K) Array Full (16K) Array
At GND Normal Read/Write Operations
▉Memory Organization
T24C02A, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing.
T24C04A, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing.
T24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing.
T24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.
▉Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (e to Figure 1 on page 5). Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (e to Figure 2 on page 5).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read quence, the stop command will place the EEPROM in a standby power mode (e Figure 2 on page 5).
ACKNOWLEDGE: All address and data words are rially transmitted to and from the EEPROM in 8-bit words. The EEPROM nds a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.
蛋白粉功效STANDBY MODE: The T24C02A/T24C04A/T24C08A/T24C16A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system ret, any two-wire part can be ret by following the steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
●Figure 1: Data Validity
l Figure 2: Start and Stop Definition
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●Figure 3: Output Acknowledge
凉拌素什锦▉Device Addressing
检查妇科病需要做哪些项目The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (e to Figure 4 on page 8).
The device address word consists of a mandatory "1", "0" quence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. The 3 bits must compare to their corresponding hardwired input pins.
The 4K EEPROM only us the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no connect.
The 8K EEPROM only us the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.
The 16K does not u any device address bits but instead the 3 bits are ud for memory page addressing. The page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect.
The eighth bit of the device address is the read/write operation lect bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state.
▉Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write quence with a stop condition. At this time the EEPROM enters an internally timed write cycle, t WR, to the
