M24256
M24128
256/128 Kbit Serial I²C Bus EEPROM
Without Chip Enable Lines
2C Extended Addressing Array s Compatible with I
2C Serial Interface
s Two Wire I
Supports 400kHz Protocol
s Single Supply Voltage:
–4.5V to 5.5V for M24xxx
–2.5V to 5.5V for M24xxx-W
s Hardware Write Control
s BYTE and PAGE WRITE (up to 64 Bytes)
s RANDOM and SEQUENTIAL READ Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behavior
s More than 100,000 Era/Write Cycles
s More than 40 Year Data Retention
DESCRIPTION
The I2C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits (M24256) and 16Kx8 bits
(M24128), and operate down to 2.5V (for the -W
version of each device).
The M24256B, M24128B and M24256A are also Array available, and offer the extra functionality of the
chip enable inputs. Plea e the parate data
sheets for details of the products.
The M24256 and M24128 are available in Plastic
logo注册商标Dual-in-Line and Plastic Small Outline packages.
The memory devices are compatible with the
I2C extended memory standard. This is a two wire
Table 1. Signal Names
SDA Serial Data/Address Input/
Output
SCL Serial Clock
WC Write Control
V CC Supply Voltage
V SS Ground
June 2001
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M24256, M24128
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rial interface that us a bi-directional data bus and rial clock. The memory carries a built-in 4-bit unique Device Type Identifier code (1010) in accordance with the I 2C bus definition.
The memory behaves as a slave device in the I 2C protocol, with all memory operations synchronized by the rial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory in-rts an acknowledge bit during the 9th bit time,following the bus master’s 8-bit transmission.When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and af-ter a NoAck for READ.
Power On Ret: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent write operations during power up, a Power On Re-t (POR) circuit is included. The internal ret is held active until the V CC voltage has reached the POR threshold value, and all operations are dis-abled – the device will not respond to any com-mand. In the same way, when V CC drops from the operating voltage, below the POR threshold value,all operations are disabled and the device will not
respond to any command. A stable and valid V CC must be applied before applying any logic signal.SIGNAL DESCRIPTION Serial Clock (SCL)
The SCL input pin is ud to strobe all data in and out of the memory. In applications where this line is ud by slaves to synchronize the bus to a slow-
Table 2. Absolute Maximum Ratings 1
Note:1.Except for the rating “Operating Temperature Range”, stress above tho listed in the Table “Absolute Maximum Ratings” may
cau permanent damage to the device. The are stress ratings only, and operation of the device at the or any other conditions above tho indicated in the Operating ctions of this specification is not implied. Exposure to Absolute Maximum Rating condi-tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.2.IPC/JEDEC J-STD-020A
福书3.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω)
Symbol Parameter
Value Unit T A Ambient Operating Temperature –40 to 125°C T STG Storage Temperature
–65 to 150
°C T LEAD Lead Temperature during Soldering PDIP: 10 conds
SO: 20 conds (max) 2
260235°C V IO Input or Output range –0.6 to 6.5V V CC Supply Voltage
–0.3 to 6.5V V ESD
Electrostatic Discharge Voltage (Human Body model) 3
4000
V
M24256, M24128
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er clock, the master must have an open drain out-put, and a pull-up resistor must be connected from
the SCL line to V CC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro-nization is not employed, and so the pull-up resis-tor is not necessary, provided that the master has a push-pull (rather than open drain) output. Serial Data (SDA)
The SDA pin is bi-directional, and is ud to trans-fer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to V CC. (Figure 3 indicates how the value of the pull-up resistor can be calculated).
Write Control (WC)午睡的英文
protecting the entire contents of the memory from inadvertent era/write. The Write Control signal is ud to enable (WC=V IL) or disable (WC=V IH) write instructions to the entire memory area. When unconnected, the WC input is internally read as V IL, and write operations are allowed.
When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowl-edged.
Plea e the Application Note AN404 for a more detailed description of the Write Control feature. DEVICE OPERATION
The memory device supports the I2C protocol. This is summarized in Figure 4, and is compared with other rial bus protocols in Application Note AN1001. Any device that nds data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the rial clock for synchronization. The memory device is always a slave device in all communica-tion.
Start Condition
START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device con-tinuously monitors (except during a programming cycle) the SDA and SCL lines for a START condi-tion, and will not respond unless one is given. Stop Condition
STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communica-tion between the memory device and the bus mas-te
r. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is ud to indicate a suc-cessful byte transfer. The bus transmitter, whether it be master or slave, releas the SDA bus after nding eight bits of data. During the 9th clock pul period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits. Data Input
During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal
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M24256, M24128
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must be stable during the clock low-to-high transi-tion, and the data must change only when the SCL line is low.
Memory Addressing
To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master nds the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code is fur-ther subdivided into: a 4-bit Device Type Identifier,and a 3-bit Chip Enable “Address” (0, 0, 0).
To address the memory array, the 4-bit Device Type Identifier is 1010b.
The 8th bit is the RW bit. This is t to ‘1’ for read and ‘0’ for write operations. If a match occurs on the Device Select Code, the corresponding mem-ory gives an acknowledgment on the SDA bus dur-ing the 9th bit time. If the memory does not match the Device Select Code, it delects itlf from the bus, and goes into stand-by mode.
2Table 3. Device Select Code 1
Note:1.The most significant bit, b7, is nt first.
Device Type Identifier
Chip Enable
RW b7
b6b5b4b3b2b1b0Device Select Code
1
1
RW
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M24256, M24128
There are two modes both for read and write.The are summarized in Table 4 and described later. A communication between the master and the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Ta-
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ble 5) is nt first, followed by the Least significant Byte (Table 6). Bits b15 to b0 form the address of the byte in memory. Bit b15 is treated as a Don’t Care bit on the M24256 memory. Bits b15 and b14are treated as Don’t Care bits on the M24128memory.
Table 4. Operating Modes
Note:1.X = IH IL .
Mode
RW bit WC 1Data Bytes
Initial Sequence
Current Address Read 1X 1START, Device Select, RW = ‘1’
Random Address Read 0X 1START, Device Select, RW = ‘0’, Address 1X reSTART, Device Select, RW = ‘1’
Sequential Read 1X ≥ 1Similar to Current or Random Address Read Byte Write 0V IL 1
START, Device Select, RW = ‘0’
Page Write
V IL
≤ 64START, Device Select, RW = ‘0’
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
M24256, M24128
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Write Operations
公共汽车上Following a START condition the master nds a Device Select Code with the RW bit t to ’0’, as shown in Table 4. The memory acknowledges this,and waits for two address bytes. The memory re-sponds to each address byte with an acknowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC input pin is taken high. Any write command with WC=1 (during a period of time from the START
condition until the end of the two address bytes)will not modify the memory contents, and the ac-companying data bytes will not be acknowledged,as shown in Figure 5.Byte Write
In the Byte Write mode, after the Device Select Code and the address bytes, the master nds one data byte. If the addresd location is write protected by the WC pin, the memory replies with a NoAck, and the location is not modified. If, in-stead, the WC pin has been held at 0, as shown in Figure 6, the memory replies with an Ack. The master terminates the transfer by generating a STOP condition.Page Write
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The Page Write mode allows up to 64 bytes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory:that is the most significant memory address bits (b14-b6 for the M24256 and b13-b6 for the M24128) are the same. If more bytes are nt than
Table 5. Most Significant Byte
Note:1.b15 is treated as Don’t Care on the M24256 ries.
b15 and b14 are Don’t Care on the M24128 ries.
Table 6. Least Significant Byte
b15
b14
b13
b12
传统服装b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
