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Features关羽的性格特点
•Low-voltage and Standard-voltage Operation, VCC = 2.7V–5.5V •Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K), or 2048 x 8 (16K)•Two-wire Serial Interface
•Schmitt Trigger, Filtered Inputs for Noi Suppression •Bidirectional Data Transfer Protocol •400 kHz Compatibility
•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed
•Self-timed Write Cycle (5 ms max)•
High Reliability
–Endurance: One Million Write Cycles –Data Retention: 100 Years –ESD Protection: >3000V
Description
The AT24C01A/02SC/04SC/08SC/16SC provide 1024/2048/4096/8192/16384 bits of rial, electrica
lly-erasable, and programmable read-only memory (EEPROM) orga-nized as 128/256/512/1024/2048 words of 8 bits each. The devices are optimized for u in smart card applications where low-power and low-voltage operation may be esntial. The devices are available in veral standard ISO 7816 smart card modules (e Ordering Information, pages 12–13). All devices are functionally equivalent to Atmel rial EEPROM products offered in standard IC packages (PDIP , SOIC, TSSOP ,MAP), with the exception of the slave address and write protect functions, which are not required for smart card applications.Figure 1. Card Module Contact
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我有一个梦AT24C01ASC/02SC/04SC/08SC/16SC
1610B –SEEPR –04/04
Figure 2. Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is ud to positive edge clock data into each EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for rial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.
Memory Organization
AT24C01ASC, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-bit data word address for random word addressing.
AT24C02SC, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing.
Absolute Maximum Ratings
*NOTICE:
Stress beyond tho listed under “Absolute Maximum Ratings ” may cau permanent dam-age to the device. This is a stress rating only and functional operation of the device at the or any other conditions beyond tho indicated in the operational ctions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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AT24C01ASC/02SC/04SC/08SC/16SC
1610B –SEEPR –04/04
独具慧眼意思
AT24C04SC, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing.
AT24C08SC, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address random word addressing.
AT24C16SC, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address random word addressing.
Pin Capacitance
DC Characteristics
AC CC 2.V IL min and V IH max are reference only and are not tested.
AC Characteristics
Table 2. Pin Capacitance (1)
Applicable over recommended operating range from T = 25°C, f = 1.0 MHz, V = +2.7V
Table 3. DC Characteristics (1)
(1)
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AT24C01ASC/02SC/04SC/08SC/16SC
百合花茶1610B –SEEPR –04/04
A CC (unless otherwi noted)2.This parameter is characterized and is not 100% tested.
Device Operation
CLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL-low time periods (e Figure 3 on page 5). Data changes during SCL-high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (e Figure 4 on page 6).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read quence, the Stop command will place the EEPROM in a standby power mode (e Figure 4 on page 6).
ACKNOWLEDGE: All address and data words are rially transmitted to and from the EEPROM in 8-bit words. Each word requires the receiver to acknowledge that it has received a valid command or data byte. During the transmission of commands from the host to the EEPROM, the EEPROM will nd a zero to the host to acknowledge that it has received a valid command byte. This occurs on the ninth clock cycle of the com-mand byte. During read operations, the host will nd a zero to the EEPROM to acknowledge that it has received a valid data byte and that it requests the next quen-tial data byte to be transmitted during the subquent eight clock cycles. This occurs on the ninth clock cycle of the data byte. If the host does not transmit this acknowledge bit,the EEPROM will disable the read operation and return to standby mode.
STANDBY MODE: The AT24C01ASC/02SC/04SC/08SC/16SC feature a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss, or system ret, any two-wire part can be ret by following the steps:1.Clock up to 9 cycles.
2.Look for SDA high in each cycle while SCL is high.
3.Create a start condition as SDA is high.
Table 4. AC Characteristics (1) (Continued)
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AT24C01ASC/02SC/04SC/08SC/16SC
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Timing Diagrams
Bus Timing
Figure 1. Bus Timing
Note:SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 2. Write Cycle Timing
Notes:
1.The write cycle time t WR is the time from a valid stop condition of a write quence to
the end of the internal clear/write cycle.2.SCL: Serial Clock, SDA: Serial Data I/O
Data Validity
Figure 3.
Data Validity
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AT24C01ASC/02SC/04SC/08SC/16SC
平菇种植技术1610B –SEEPR –04/04
Start and Stop Definition
Figure 4. Start and Stop Definition
Output Acknowledge
Figure 5.
Output Acknowledge
