Proximity Effect Modeling除夕祝福文案
Colin McAndrew
Freescale Semiconductor
Tempe, AZ
Abstract
The book (Operation and Modeling of the MOS Transistor, 3rd Edition, by Yannis Tsividis and Colin McAndrew, Oxford University Press, 2011) discuss proximity effects (well proximity and stress effects) in Chap. 9. The models of the effects are highly empirical and are constantly changing, so no specific model forms were provided (e p. 581, Chap. 9); some details of prently ud proximity effect models are provided here.
Well Proximity Effect Model
The well proximity effect (WPE) can significantly alter the characteristics of MOS transistors [1][2], and if not factored into design can cau circuits to fail. The cau of the effect and how it modifies the stru
cture of a device are shown in Fig. 1 and Fig. 2, respectively. During implantation of the dopants that form the wells in which MOS transistors are formed, photoresist is patterned outside of the regions to prevent the ions penetrating into regions where they are meant to be excluded. However, ions that impinge on photoresist interact with the atoms that form the photoresist. The interactions are statistical, and “scatter” the ions at random angles. Multiple scattering events drain the ions of their kinetic energy, so they stop within the photoresist (which is subquently stripped from the silicon wafer surface). For ions that impinge near the edge of the photoresist, they can scatter back out of the photoresist, and then become embedded in the silicon adjacent to the photoresist edge. Well doping is therefore not uniform across a wafer, but is enhanced in regions adjacent to the edges of a well, to a distance of about 1 µm [1][2]. This is shown diagrammatically in Fig. 2. Note that ion implantation is often done at a small angle to vertical to a wafer (as shown in Fig. 1), to prevent ions from avoiding scattering and penetrating too deeply by “channeling” along open paths in the silicon lattice. This may give the impression that the well doping enhancement is from ions that are “reflected” from the photoresist edge. This is incorrect; the scattering occurs within the photoresist and is obrved even if the implantation angle is vertical.
Fig. 1Well proximity effect cau. Scattering in the photoresist augments well doping near the well edge.
As is discusd at length in the book, the net bulk doping concentration is one of the key physical parameters than controls the operation of MOS transistors. Therefore it should be apparent that the proximity of a transistor to a well edge, which changes its bulk doping, can affect its behavior signific孕妇可以吃桂圆
antly. Prior to about the 0.25 µm technology node the overall size of transistors meant they could not be placed clo enough to a well edge for the enhanced doping level to affect their behavior. For technology nodes below that WPE has become an important issue.
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There are two aspects to understanding and modeling WPE: the adjacency of a transistor to well edges, which affects the overall enhancement of the net doping in a device; and the effect of the net doping enhancement on transistor electrical behavior, via model parameters. Fig. 3 shows a MOS transistor in a simple rectangular well. The notation SC is for the spacing of a well edge to the edge of the gate, and there are four different spacings, 1
SC shown in Fig. 3. To
SC through 4
integrate the effect of the additional well do from each adjacent edge on every model parameter is a daunting task, and it blurs the line between layout extraction and modeling and simulation, which are generally parate steps in an IC design flow. Therefore the approach taken for WPE modeling has been to parate the steps of extracting effective indicators (“moments”) of the additional well doping from the device layout, and of modeling the change in device behavior bad on the mome
nts. This enables implementation of WPE across different types of models; for example, for a surface potential-bad model the WPE can be handled by making the FB
V parameter a function of the moments, and for a threshold voltage-
bad model 0T V can be made a function of the moments.
Fig. 2Well doping varies with distance from the well edge.
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Fig. 3Layout of a MOS transistor with respect to well edges.
Empirically, if spacing to a well edge is s (measured normal to the edge), and a reference well edge to gate edge length to normalize this distance is ref SC , the following do basis functions for the moment calculations have been found to provide the best fit to experimental data [3]
(1)
ref ref SC s ref C SC s ref
B ref A e S
C s s f e SC s s f s SC s f 20102)()()(−−==⎟⎟⎠⎞⎜⎜⎝⎛= where the first is the obrved asymptotic behavior for large s and the other terms provide corrections for smaller s . To implement corrections for the WPE, MOS transistor models are to expected to accept as “instance” parameters three quantities, SCA , SCB , and SCC , that are the averages of the above basis functions. The are computed by integrating the functions over the area of the gate, which gives the total contribution from each do function, and then normalizing each integral by dividing by the gate area,
(2) dxdz z x s f WL f W W L ∫∫−=220)),((1.
The normalization is necessary becau although the additional do from the left well edge in Fig. 3
will have certain maximum value, as the gate length of the transistor increas the portion of the transistor affected by this do decreas. For the purpo of modeling the overall change in device behavior should also decrea, hence the need to divide by the gate area.
There are four edges, right, bottom, left and top, in Fig. 3 that contribute extra doping to the well under the gate of the transistor. The moments of the do basis functions are then
(3) ⎟⎟⎟⎠⎞⎜⎜⎜⎝⎛+++=∫
∫∫∫++++ds s f L ds s f W ds s f L ds s f W LW SCA W SC SC A L SC SC A W SC SC A L SC SC A 44332211)()()()(1 (4) ⎟⎟⎟⎠⎞⎜⎜⎜⎝⎛+++=∫
汉字研究报告∫∫∫++++ds s f L ds s f W ds s f L ds s f W LW SCB W SC SC B L SC SC B W SC SC B L SC SC B 44332211)()()()(1 (5) ⎟⎟⎟⎠⎞⎜⎜⎜⎝⎛+++=∫
∫∫∫++++ds s f L ds s f W ds s f L ds s f W LW SCC W SC SC C L SC SC C W SC SC C L SC SC C 44332211)()()()(1 where the spacing s is measured perpendicular to the well edge. Note that the quantities SCA , SCB , and SCC depend only on the layout geometries of the transistor and the well edges, and are not directly tied to parameters such as threshold voltage or body effect coefficient. Th
ey are extracted from the layout and then pasd to a MOS transistor model, which is then expected to make appropriate modifications to parameters.
The expressions (3) through (5) are written in integral form to emphasize that they are averages over the gate area; when actually extracted from layout clod form solutions are ud. Not all transistors have as simple layouts as shown in Fig. 3, and in practice corner contributions also need to be included. Details of how to compute SCA , SCB , and SCC for complex layouts, including multi-finger transistors, are provided in [4].山东专科分数线
The cond step in handling the WPE is for a model to u the SCA , SCB , and SCC instance parameters to make appropriate adjustments. Although it would appear that the simplest way of doing this is do modify the parameter associated with N this is not done in practice. Experimentally, the threshold voltage, body effect coefficient, and mobility are
草莓寄居蟹obrved to vary with well proximity. Rather than tie the first two together through A N they are kept parate and have parate WPE variation models. This gives greater flexibility in fitting experimental data. The forms ud in BSIM4, which have been adopted in other models, are [5]
(6)
()SCC W SCB W SCA K V V EC EB WE VT noWPE T T +++=0,00 (7)
()SCC W SCB W SCA K EC EB WE noWPE +++=2γγ (8) ()()SCC W SCB W SCA K EC EB WE U noWPE +++=01µµ
where WE VT K 0, WE K 2, WE U K 0, EB W , and EC W are fitting parameters, and the added subscript “noWPE ” is ud to indicate the value of a parameter in the abnce of the WPE. For charge sheet models, the threshold voltage shift (6) is implemented as a shift in FB V which, from (4.7.19), is equivalent.
Fig. 4 shows the threshold voltage shift from the well proximity effect as a function of the well-edge to gate-edge spacing for a 90 nm technology [2]. The amount of the threshold shift reaches veral 10’s of mV, which can be significant if the supply voltage is of order 1.2 V, and is still a few mV even when the well edge is 1 µm from the edge of the gate.
Fig. 4 Threshold voltage shift vs. well spacing.
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