UCC27210UCC27211
ZHCS501E –NOVEMBER 2011–REVISED AUGUST 2013
120V 升压，4A 峰值电流，高频高侧和低侧驱动器
查询样片:UCC27210,UCC27211
特性
应用范围
•
用独立输入驱动高侧和低侧配置中的两个N 通道金•针对电信，数据通信和商用的电源属氧化物半导体场效应晶体管(MOSFET)•半桥和全桥转换器•最大引导电压120V 直流•推挽转换器
•4A 吸收，4A 源输出电流•高电压同步降压型转换器•0.9Ω上拉和下拉电阻
•两开关正激式转换器•输入引脚能够耐受-10V 至20V 的电压，并且与电•有源箝位正激式转换器源电压范围无关
•
D 类音频放大器
•晶体管-晶体管逻辑电路(TTL)或伪CMOS 兼容输入版本
说明
•8V 至17V VDD 运行范围，（绝对最大值20V ）UCC27210和UCC27211驱动器基于常见的
•7.2ns 上升和5.5ns 下降时间（采用1000pF 负载UCC27200和UCC27201MOSFET 驱动器，但是对时）
性能进行了几项重大改进。峰值输出上拉和下拉电流•快速传播延迟时间（典型值18ns)已经被增加至4A 拉电流和4A 灌电流，并且上拉和下•2ns 延迟匹配
拉电阻已经被减少至0.9Ω，因此可以在MOSFET 的•用于高侧和低侧驱动器的对称欠压闭锁功能
米勒效应平台转换期间用尽可能小的开关损耗来驱动大•
可提供全部行业标准封装（小外形尺寸集成电路功率MOSFET 。现在，输入结构能够直接处理-10(SOIC)-8封装，PowerPAD™SOIC-8，4mm x VDC ，这增加了稳健耐用性，并且可实现与栅极驱动4mm 小外形尺寸无引线(SON)-8封装和4mm x 变压器的直接对接，而无需使用整流二极管。此输入4mm SON-10）
与电源电压无关，并且具有一个20V 的最大额定值。
•
-40℃至140℃的额定温度范围
典型应用图
Plea be aware that an important notice concerning availability,standard warranty,and u in critical applications of Texas Instruments miconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
UCC27210
UCC27211
ZHCS501E–NOVEMBER2011–REVISED 说明（续）
UCC27210/1的开关节点（HS引脚）能够处理-18V最大电压，这可保护高侧通道不受固有负电压所导致的寄生电感和离散电容的损坏。UCC27210（伪CMOS输入）和UCC27211（TTL输入）已经增加了滞后，从而使得到模拟或数字脉宽调制(PWM)控制器的接口具有增强的抗扰度。
低端和高端栅极驱动器是独立控制的，并在彼此的接通和关断之间实现了至2ns的匹配。
监理月报
由于在芯片上集成了一个额定电压为120V的自举二极管，因此无需采用外部分立式二极管。为高端和低端驱动器提供了欠压闭锁功能，如果驱动电压低于额定的阀值电压，则提供对称接通/关闭运行方式，并且强制输出为低电平。
这两款器件均采用8引脚SOIC(D)，PowerPad™SOIC-8(DDA)，4mm x4mm SON-8(DRM)和SON-10(DPR)封装。
The devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
PACKAGED DEVICES(1)
INPUT
TEMPERATURE RANGE T A=T J PowerPAD™
COMPATIBILITY SOIC-8(D)(2)SON-8(DRM)(3)SON-10(DPR)(4)
SOIC-8(DDA)(2)
Pudo CMOS UCC27210D UCC27210DDA UCC27210DRM UCC27210DPR -40°C to140°C
TTL UCC27211D UCC27211DDA UCC27211DRM UCC27211DPR (1)The products are packaged in Lead(Pb)-Free and green lead finish of PdNiAu which is compatible with MSL level1at255°C to
260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
(2)D(SOIC-8)and DDA(Power Pad™SOIC-8)packages are available taped and reeled.Add R suffix to device
UCC27210ADR/UCC27211ADR)to order quantities of2,500devices per reel.
(3)DRM(SON-8)package comes either in a small reel of250pieces as part number UCC27210ADRMT/UCC27211ADRMT,or larger reels
of3000pieces as part number UCC27210ADRMR/UCC27211ADRMR.
(4)DPR(SON-10)package comes either in a small reel of250pieces as part number UCC27210ADPRT/UCC27211ADPRT,or large reels
of3000pieces as part number UCC27210ADPRR/UCC27211ADPRR.
UCC27210
UCC27211 ZHCS501E–NOVEMBER2011–REVISED AUGUST2013 ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range(unless otherwi noted)
MIN MAX UNIT Supply voltage range,V DD(1),V HB-V HS-0.320
Input voltages on LI and HI,V LI,V HI-1020
DC-0.3V DD+0.3
Output voltage on LO,V LO
Repetitive pul<100ns(2)-2V DD+0.3
DC V HS–0.3V HB+0.3V Output voltage on HO,V HO
Repetitive pul<100ns(2)V HS-2V HB+0.3
DC-1115
Voltage on HS,V HS
Repetitive pul<100ns(2)-(24V-VDD)115
Voltage on HB,V HB-0.3120
Human Body Model(HBM)2
ESD kV
Field Induced Charged Device Model
1
(FICDM)
Operating virtual junction temperature range,T J-40150
Storage temperature,T STG-65150°C
Lead temperature(soldering,10c.)300
枯瘦的近义词(1)All voltages are with respect to VSS unless otherwi noted.Currents are positive into,negative out of the specified terminal.
(2)Verified at bench characterization.VDD is the value ud in an application design.
RECOMMENDED OPERATING CONDITIONS
all voltages are with respect to V SS;currents are positive into and negative out of the specified terminal.–40°C<T J=T A< 140°C(unless otherwi noted)
PARAMETER MIN TYP MAX UNIT Supply voltage range,V DD,V HB-V HS81217
Voltage on HS,V HS-1105
V Voltage on HS,V HS(repetitive pul<100ns)-(24V-VDD)110
V HS+8,V HS+17,
Voltage on HB,V HB
V DD–1115
Voltage slew rate on HS50V/ns Operating junction temperature range-40140°C
UCC27210
UCC27211
ZHCS501E–NOVEMBER2011–REVISED THERMAL INFORMATION
UCC27210/11(1)
THERMAL METRIC D DDA UNITS
8PINS8PINS
θJA Junction-to-ambient thermal resistance(2)111.837.7
θJCtop Junction-to-ca(top)thermal resistance(3)56.947.2
θJB Junction-to-board thermal resistance(4)53.09.6
°C/W
ψJT Junction-to-top characterization parameter(5)7.8 2.8
ψJB Junction-to-board characterization parameter(6)52.39.4
θJCbot Junction-to-ca(bottom)thermal resistance(7)n/a 3.6
(1)For more information about traditional and new thermal metrics,e the IC Package Thermal Metrics application report,SPRA953.
(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as
specified in JESD51-7,in an environment described in JESD51-2a.
(3)The junction-to-ca(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific JEDEC-
standard test exists,but a clo description can be found in the ANSI SEMI standard G30-88.
(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature,as described in JESD51-8.
(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(ctions6and7).
(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(ctions6and7).
(7)The junction-to-ca(bottom)thermal resistance is obtained by simulating a cold plate test on the expod(power)pad.No specific
射手女处女男JEDEC standard test exists,but a clo description can be found in the ANSI SEMI standard G30-88.
THERMAL INFORMATION
UCC27210/11(1)
THERMAL METRIC DRM DPR UNITS
8PINS10PINS
θJA Junction-to-ambient thermal resistance(2)33.936.8
θJCtop Junction-to-ca(top)thermal resistance(3)33.236.0
θJB Junction-to-board thermal resistance(4)11.414.0
°C/W
ψJT Junction-to-top characterization parameter(5)0.40.3
ψJB Junction-to-board characterization parameter(6)11.714.2
小学一年级看图写话图片全集
θJCbot Junction-to-ca(bottom)thermal resistance(7) 2.3 3.4
(1)For more information about traditional and new thermal metrics,e the IC Package Thermal Metrics application report,SPRA953.
(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as
specified in JESD51-7,in an environment described in JESD51-2a.
(3)The junction-to-ca(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific JEDEC-
standard test exists,but a clo description can be found in the ANSI SEMI standard G30-88.
(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature,as described in JESD51-8.
那一刻我长大了作文(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(ctions6and7).
(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(ctions6and7).
(7)The junction-to-ca(bottom)thermal resistance is obtained by simulating a cold plate test on the expod(power)pad.No specific
JEDEC standard test exists,but a clo description can be found in the ANSI SEMI standard G30-88.
UCC27210
UCC27211 ZHCS501E–NOVEMBER2011–REVISED AUGUST2013 ELECTRICAL CHARACTERISTICS生活体验
V DD=V HB=12V,V HS=V SS=0V,no load on LO or HO,T A=T J=-40°C to140°C,(unless otherwi noted)
PARAMETER TEST CONDITION MIN TYP MAX UNITS
Supply Currents
I DD V DD quiescent current V(LI)=V(HI)=0V0.050.0850.17
I DDO UCC27210 2.6 5.2
V DD operating current f=500kHz,C LOAD=0
UCC27211 2.5 5.2mA
I HB Boot voltage quiescent current V(LI)=V(HI)=0V0.0150.0650.1
I HBO Boot voltage operating current f=500kHz,C LOAD=0 2.5 5.0
I HBS HB to V SS quiescent current V(HS)=V(HB)=115V0.0005 1.0µA
I HBSO HB to V SS operating current f=500kHz,C LOAD=00.07 1.2mA
Input
V HIT Input voltage threshold UCC27210 4.2 5.0 5.8
UCC27210(DDA only) 4.2 5.0 5.9
V LIT Input voltage threshold UCC27210 2.4 3.2 4.0V
UCC27210(DDA only) 2.4 3.2 4.0
V IHYS Input voltage hysteresis 1.8
UCC27210
R IN Input pulldown resistance102kΩ
V HIT Input voltage threshold UCC27211 1.9 2.3 2.7
UCC27211(DDA only) 1.9 2.3 2.8
V
小鸟怎么养>拔河比赛游戏规则V LIT Input voltage threshold UCC27211 1.3 1.6 1.9
UCC27211(DDA only) 1.3 1.6 2.1
V IHYS Input voltage hysteresis700mV
UCC27211
R IN Input pulldown resistance68kΩ
Under-Voltage Lockout(UVLO)
V DDR V DD turn-on threshold 6.27.07.8
DDA only 5.87.08.1
V DDHYS Hysteresis0.5
V
V HBR V HB turn-on threshold 5.6 6.77.9
DDA only 5.3 6.78.0
V HBHYS Hysteresis 1.1
Bootstrap Diode
V F Low-current forward voltage I VDD-HB=100µA0.650.8
V
V FI High-current forward voltage I VDD-HB=100mA0.850.95
R D Dynamic resistance,ΔVF/ΔI I VDD-HB=100mA and80mA0.30.50.85Ω
LO Gate Driver
V LOL Low-level output voltage I LO=100mA0.050.090.19
V
V LOH High level output voltage I LO=-100mA,V LOH=V DD-V LO0.10.160.29
Peak pull-up current(1)V LO=0V 3.7
A Peak pull-down current(1)V LO=12V 4.5
HO GATE Driver
V HOL Low-level output voltage I HO=100mA0.050.090.19
V
V HOH High-level output voltage I HO=-100mA,V HOH=V HB-V HO0.10.160.29
Peak pull-up current(1)V HO=0V 3.7
A Peak pull-down current(1)V HO=12V 4.5
(1)Ensured by design.
