An 11.5-ENOB 100-MS/s 8mW Dual-Reference SAR ADC in 28nm CMOS
Michael Inerfield, Abhishek Kamath, Feng Su, Jason Hu, Xinyu Yu, Victor Fong, Omar Alnaggar, Fang Lin and Tom Kwan
Broadcom Corporation, San Jo, CA, USA E-mail: Abstract Recent publications have demonstrated ADCs with ENOB > 11, sampling frequencies > 50MHz, with power < 50mW, making the SAR ADC architecture an attractive alternative to the traditional pipeline. This paper prents a production quality 11.5 ENOB, 89dB SFDR, 100MS/s SAR ADC that, including the voltage reference and digital calibration circuitry, consumes 8mW and us 0.1mm2 in 28nm CMOS. It us a unique dual-reference, dual unit-cap architecture with a regulated DAC switch, providing a 2Vppd input swing while utilizing a low-voltage transistor implementation for the core ADC. Keywords: SAR, ADC Introduction In recent years, advanced CMOS process have provided incread device speed and passive matching properties while requiring lower power supply voltages to meet reliability and leakage requirements. This trend has made the Successive Approximation (SAR) ADC a competitive architecture choice in high-speed, medium-resolution applications. The power of a SAR ADC scales well with process compared to architectures that u op amps. More recently, process improvements have enabled SARs that can achieve higher speed and finer precision [1]-[2]. This paper prents an 1
1.5 ENOB, 100 MS/s, 8mW SAR ADC implemented in a standard 28nm CMOS process. ADC Architecture The SAR ADC prented in this work (Fig. 1) is a single-lane, dual-reference, split-capacitor DAC topology [3] using top-plate bootstrapped sampling and two types of unit caps. It supports a 2Vppd input with a 0.8V common mode and converts 16 bits with one bit of overrange. Concerns for noi and power drove the need to maximize the signal swing supported by the ADC, while avoiding voltage levels that would necessitate the u of IO devices in the DAC switches and, thus, reduce the SAR’s conversion speed. A top-plate sampling structure was chon to avoid comparator noi gain and isolate high-voltage requirements at the comparator input. There are typically two dominant sources of noi in a switched-capacitor SAR ADC: kT/C noi during sampling of the input onto the DAC array and comparator thermal noi. To minimize power and area, an optimized design should t the DAC array capacitance to meet the requirement t by kT/C noi. In high-resolution SARs, however, the matching requirement dominates, and many designs size up the capacitor array to meet it. There is strong incentive to avoid this as the size of the capacitor array has a proportional effect on both the overall size and the power of the ADC. This ADC mitigates matching concerns by employing a foreground calibration method that us the LSB back end to measure the relative weights of the MSB capacitors. The data is postprocesd during normal operation by on-chip circuitry that applies the MSB weights determined in the offline calibratio
n. Calibration The five MSBs are calibrated in this architecture, confining the matching requirement to the 11-bit ction of the array. The calibration boundary provides a natural place to parate the DAC array into two parately optimized parts. In the MSB ction, a high-density finger capacitor structure was chon to keep the core ADC area low. Becau the MSB capacitance only has to be broken into 62 units per side, the unit ud to build this part of the array can be made den. The much smaller capacitance of the LSB ction can then be constructed from less den units, which are conducive to being divided into the 512 required pieces. For an input capacitance of 1.25pF to meet sampling noi requirements, a 15-bit array requires a 76aF unit capacitor, which is difficult to implement. To achieve 10-bit matching, Vref1/4 was chon
Fig. 1 ADC architecture.
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2014 Symposium on VLSI Circuits Digest of Technical Papers
as the LSB ction reference, allowing the unit capacitor to be scaled up by 4. The array has 1.25pF on each single-ended side, with 1pF allocated to the MSB ction and 250fF for the total LSB capacitance. Becau the array is split into two ctions, redundancy is needed to absorb mismatch
between the two types of capacitor and reference values. Calibration of the MSB capacitors for matching requires a redundant conversion anyway, so adding an overrange conversion as the first bit of the LSB array has no extra cost. For the top-plate sampling structure, the reference experiences attenuation by the divider with the summing-junction parasitic that the signal does not. An advantage of this is the comparator noi does not get amplified when referred to the input. The reference voltage, however, must be larger than it would have to be in the bottom-plate sampling structure. Summing junction parasitics tend to be large (~200fF) due to the low-noi comparator and DAC routing distance, thus the first reference must be pushed to 1.4V, posing a reliability problem for core transistor DAC switches. To address this problem, the MSB DAC switches contain a small level shifter powered by an on-chip LDO as shown in Fig. 1. This is achieved using an inverter made out of an IO PMOS (M1) with Vdd=Vref1=1.4V and an IO native NMOS (M2) which has a 0.4V VSS. Native M2 can be turned on by a core inverter, even though its source is elevated. M1’s channel length is sized to minimize leakage current from the LDO when it is off. For the MSB switch, the path to turn off M3 is critical, as rapid turn off prevents a large crowbar current from flowing through the switch from the reference. M3 turn-off is fast becau M1 gets 1.4V Vsg. M3 turn on is slower due to limited M2 Vgs as well as its large minimum channel length. This switch is only ud for the 5 MSBs, as the split array allows the 11 LSBs to u a lower reference voltage and core
switches. The level shifter part of the MSB switches requires IO devices, but the cascoded MSB switches (M3-M6) are all core devices, which minimizes their Cgs. Even though the overrange can compensate for reference droop during the conversion, M3 and M4 Cgs and switch leakage both increa reference power, as charge lost in the reference bypass capacitor must be replenished every clock cycle. Measurement Results The ADC is fabricated in a 28nm process (die photo shown in Fig. 2) and occupies an area of 0.10mm2. It includes all circuits needed for a production design: the core ADC, voltage reference, LDO, and the calibration engine. A 1.0V supply is ud for the ADC core, and a 1.8V supply is ud for the reference and LDO. The total power consumed is 8.0mW. ADC core power is 4.8mW including the comparator and calibration engine, and the reference and LDO power is 3.2mW. The chip also includes an on-chip differential input buffer to drive the ADC. Fig. 3
shows PSDs for low-frequency and Nyquist performance. Performance vs. input frequency is shown in Fig. 4. At low frequency, the ADC achieves 71dB SNDR and 89.2dB SFDR, and at Nyquist, 67.1dB SNDR and 75.8dB SFDR. The ADC achieves 27.7fJ/step near DC and 43.2fJ/step at Nyquist, including LDO, reference, and calibration engine power.
PSD for fin=1.5MHz 0 SNR = 71.12dB Power (dB) -50 SNDR = 70.95dB SFDR = 89.22dB
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Fig. 4 ADC performance vs. input frequency. TABLE I PERFORMANCE SUMMARY AND COMPARISON [1] Kapusta [2] Morie This (ISSCC-2013) (ISSCC-2013) Work Architecture Technology (CMOS, nm) Resolution (bits) Sample rate (MS/s) Peak SNDR low freq (dB) Peak SNDR, Nyq (dB) Power (mW) FOM (fJ/step), Nyq w/ voltage ref w/o voltage ref Area (mm2) SAR 65 14 80 73.6 71.3 35.1 146.2 129.5 0.55 SAR 90 14 50 71 69 4.2 (unknown) 36.1 0.10 SAR 28 15 100 71.0 67.1 8.0 43.2 25.9 0.10
References
[1] R. Kapusta, J. Shen, et al., “A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS,” ISSCC Dig. Tech Papers, vol. 1, pp. 472 -474, Feb 2013. [2] T. Morie, T. Miki, et al., “A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR Enhancement Techniques Utilizing Noi,” ,” ISSCC Dig. Tech Papers, vol. 1, pp. 272 -274, Feb 2013. [3] B. P. Ginsburg and A. P. Chandrakasan "An energy-efficient charge recycling approach for a SAR converter with capacitive DAC," Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, pp. 184 -187, 2005.
Fig. 2 Die photo. Total area = 0.1mm2
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