婴儿放屁臭是什么原因What is Flip Chip?
Flip Chip (FC) is not a specific package (like SOIC), or even a package type (like BGA). Flip Chip describes the
method of electrically connecting the die to the package carrier. The package carrier, either substrate or leadframe,
options are: eutectic (63%Sn, 37%Pb) or high lead (95%Pb,
solder bumped die is attached to a substrate by a solder reflow
process, very similar to the process ud to attach BGA balls to
cially engineered epoxy that fills the area between the die and the carrier, surrounding the solder bumps. It
is designed to control the stress in the solder joints caud by the difference in thermal expansion between the
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silicon die and the carrier. Once cured, the underfill absorbs the stress, reducing the strain on the solder bumps,
greatly increasing the life of the finished package. The chip attach and underfill steps are the basics of flip chip小生意赚大钱>卤水怎么保存
interconnect. Beyond this, the remainder of package construction surrounding the die can take many forms and
can generally utilize existing manufacturing process and package formats.
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Depending on the specific die and application requirements, different package level solutions are required. Thus flip chip interconnect can
Features:
• 4-12 layer build up substrates using epoxy laminate
• Target Market - Internet Workstation Processors, High Bandwidth System Communications Devices • Attached one or two piece heat spreader design for maximum thermal performance • 150 μm minimum bump pitch • Die sizes up to 26 mm
• Package sizes from 17 mm to 52.5 mm
• JEDEC MS-034 compliant, 1.0 mm pitch BGA footprint • Package solutions up to 2400 balls
FC M BGA (Flip Chip Molded BGA):
FC M BGA is the evolution of the SuperFC ® high performance flip chip solution. Capillary underfill (CUF) is replaced by molded underfill (MUF).Features:
• Enhanced electrical performance by allowing capacitors clor to the FC die • Enhanced warpage control - a more rigid structure for thin core substrates • Enhanced reliability by fully encapsulating passive components • 4-10 layer build up substrates • 150 μm minimum bump pitch • Die sizes up to 14 mm
• Body sizes from 15mm to 42.5mm
• JEDEC MS-034 compliant, 1.0mm pitch BGA footprint
fc BGA/LGA (Bare Die):
Flip chip packaging solution for most graphics, PC chipt, and low end ASIC applications.Features:
• 4-8 layer build up substrates using epoxy laminate • Bare die, Passive Attach
• 200 μm minimum bump pitch • Die sizes up to 16.7 mm
• Package sizes from 27 mm to 37.5 mm
• JEDEC MS-034 compliant, 1.0 mm pitch BGA footprint • Stacked vias • MRT
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• Motherboard TCE match (HITCE)• Low warpage
• Solid ground planes
• Clo substrate to silicon TCE match reduces stress on die surface
fc Ceramic CBGA/CLGA/CLLGA/Solder Column Interpor:Original packaging solution for flip chip products.
Features:• 5-20 layers HiTCE
• Target Market - Internet Workstation Processors, High Bandwidth System Communications Devices, Printer Applications • Lidded and unlidded versions, LGA and BGA, Passive Attach • 200 μm minimum bump pitch • Die sizes up to 21 mm
• Package sizes from 18 mm to 50 mm •
1.0 mm and 1.27 mm pitch footprint
NEW
Minimum package thickness of 0.80 mm for LGA interconnect, 1.0 mm for 0.5 mm BGA pitch and 1.2 mm for 0.8 mm BGA pitch
Proven reliability; exceeds all current handt mechanical reliability tests including: drop, bend and key punch
TS 102L 02’09
data sheet
fc CSP
Features:
Thermal Performance:
Electrical:
Reliability:
• Designed for high frequency applications • 9 - ~1000 ball counts
• Target Market - Cell Phones, Handheld Electronics, Applications where high density packaging is required, Multi-die and/or designs with passive comonents • Array strip production
• Thin core laminate or buildup substrate construction • Overmolded for handling and cond level reliability • Accommodates package sizes from 2 mm to 17 mm • Flip Chip bump pitches of 125 µm min. for peripheral, 150 µm min. for area array
• Cu Pillar flip chip interconnect for finer bond pad pitches • Available in 0.4 mm - 1.0 mm BGA ball pitch, as well as LGA interconnect
• Minimum package thickness of 0.70 mm for LGA interconnect, 0.9 mm for 0.4 mm BGA pitch, 1.0 mm for 0.5 mm BGA pitch
• Turnkey Solution - Design, bumping, bumped wafer probe, backgrind, asmbly, test
• Much better signal to noi ratio at higher frequencies (>1GHz) versus wirebonded packages
• Low inductance of flip chip bumps - short, direct signal path
• Flexible customizable substrate routing. Smaller possible body size than wirebond CSP due to additional space not required for wirebond pads Theta JA (°CW)
• 12 x 12 mm, 441 lead package with 7.5 mm x 7.5 mm die, 0.5 mm pitch, 0.45 mm mold cap • 0 LFPM, 4 layer PC board
• Junction ambient thermal resistance = 21.3 °C/W 8 x 8 mm body, 176 ld, 0.5 mm ball pitch
Simulated results @ at 100 MHz
环境日是每年的几月几日M in Max Inductance 0.34 nH 2.15 nH Capacitance 0.19 pF 0.64 pF
Resistance 22 m Ω 84 m Ω
Package Level:
中国成功• Laminate Moisture JEDEC Level 3 @ 260 °C Sensitivity
30 °C/60% RH, 192 hours • Ceramic Moisture JEDEC Level 1 @ 260 °C Sensitivity 85 °C/85% RH, 168 hours • PCT
121 °C/100% RH, 96 hours • Temp/Humidity 85 °C/85% RH, 1000 hours • High temp storage 150 °C, 1000 hours
• Temp cycle -55 °C/+125 °C, 1000 cycles Board Level:8 mm body, 64 lead, 0.33 mm PWB NSMD pad size
• Thermal cycle -40 °C/+125 °C,
1 cycle/hour, 3000 cycles • Thermal cycle -40 °C/+125 °C
2 cycles/hour, 2500 cycles 17 mm body, 1019 lead
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• Thermal cycle 0 °C/+100 °C,
1 cycle/hour, 2230 cycles
fc CSP Packages:
Amkor Technology is now offering the Flip Chip CSP (fcCSP) package -- a flip chip solution in a CSP package format. This package construction utilizes Pb-Free (or Eut. SnPb) flip chip interconnect technology, in either area array or peripheral bump layout, replacing standard wirebond interconnect. The advantages of flip chip interconnect are multiple: it provides enhanced electrical performance over standard wirebond technology, it allows for a smaller form factor due to incread routing density, and the elimination of wire-bond loops. Current wafer bump technology and flip chip asmbly process allows for peripheral flip chip bumping or area array bumping, with either solder or Cu pillar bump technology.
The fcCSP is bad on Amkor's proprietary ChipArray® BGA (CABGA) package construction, using cutting edge thin core laminate substrates. The package is asmbled in strip format, in either bare die or overmolded format, and saw singulated for manufacturing efficiency and cost minimiza-tion. Pattern plating for fine line/spaces, via-in-pad sub-strate structure, and thin core substrate panel pro
cessing allow for incread routing density and enhanced electrical performance, making fcCSP an attractive option for
advanced CSP applications where electrical performance is a critical factor.
The fcCSP is available in both thin core laminate substrate technology as well as build up (for further enhanced routing). Package size ranges from 2 mm to 17 mm, accommodating BGA ball pitches from 0.4 mm to 1.0 mm. In addition to BGA technology, the fcCSP is also available in LGA format, allowing for a lower minimum package thickness.
Applications:
T he fc CSP package is an attractive option for handheld/portable electronics where, in addition to performance, package size is critical. Some applications which have adopted fc CSP are high-performance workstations, rvers, data communication products and some emerging applica-tions such as netbooks and RF applications where electrical performance is critical. The elimination of wirebond loops allows for a low inductance connection to the die while the incread routing density enables optimized electrical paths for critical high frequency signal lines.
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visit amkor technology online for locations and to view the most current product information .
DS577F Rev Date: 05'10
