多周期路径 英文

更新时间:2023-07-22 18:50:36 阅读: 评论:0

Multicycles Exception Between Two Synchronous Clock
Domains
t_multicycle_path path_multiplier  [-tup |-hold ] [-start |-end ] -from <Start-Point> -through <ThroughPoint> -to <EndPoint>护理实习自我鉴定
Default path_multiplier: Setup 1, Hold 0.
Setup : Regarding to EndClock by Default. (-end  is the default)
Hold :  Regarding to StartClock by Default. (-start  is the default)
In single clock domain  design there is no meaning to the -start  and -end  flags. !!!Note: In ca your tup path_multiplier is X, u the path_multiplier of X-1 for hold.In any ca check out the report of your multicycles and the report exceptions (Plus the report_exceptions -ignore) results.
Table 1 describes how the check points for tup and hold timing are moved back-ward of forward depend on the -start/-end flags and the path_multiplier.
Table 1:Clock Edges in M.C .RED =
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Default
StartClock EndClock Setup
<-------->Hold  ----><----
Multicycle In Single Clock Domain
Figure 0-1.  Single Clock Domains Design
0.1  SETUP PATH_MULTIPLIER 5, HOLD REMAINS DEFAULT •t_multicycle_path -tup 5 -from CLK1 -to CLK2
without hold multiplier.FF Q Q
FF Q Q CLK1CLK2(Fast)
(Fast)delay>4 fast_clk_period
CLK1
CLK2
清晨的阳光唯美句子Setup
四年级下册英语单词表Hold Default:CLK2(0)+Thold < delay(min)                        delay(max) < CLK2(5)-Ttup
Required:
1345
20
Figure 0-2.  Setup 5, Hold default.
0.2  SETUP PATH_MULTIPLIER 5, HOLD PATH_MULTIPLIER 4•t_multicycle_path -tup 5 -from CLK1 -to CLK2
•t_multicycle_path -hold 4 -from CLK1 -to CLK2
Figure 0-3.  Setup 5, Hold 4.CLK1
CLK2
Setup
Hold  0
野鲮
1 2 3 401234
5
CLK1
CLK2
Setup
Hold  0
1 2 3 4
Examples for SLOW-to-FAST path.客气的反义词
Figure 0-4 - Figure 0-5 show the timing analysis in ca the StartClock, CLK1,  is slow clock and the EndClock, CLK2, is fast clock.裙子的英语单词
The RED text is the default and can be removed.
over的意思The GREEN text is the ur override
Figure 0-4.  Two Clock Domains Design FF Q Q
FF Q Q CLK1CLK2(Slow)(Fast)
delay>fast_clk_period
CLK1
CLK2
Setup Hold
0.3  DEFAULT
Figure 0-5 shows the default scenario:
•t_multicycle_path 1 -tup -end -from CLK1 -to CLK2•t_multicycle_path 0 -hold -start -from CLK1 -to CLK2
Figure 0-5. Default Scenario. Setup 1 (-end ) , Hold 0 (-start )Setup
Hold CLK1
CLK2

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