PRELIMINARY
WMS7130/1
NONVOLATILE DIGITAL POTENTIOMETERS WITH UP/DOWN (3-WIRE) INTERFACE,
10KOHM, 50KOHM, 100KOHM RESISTANCE
32 TAPS
WITH OPTIONAL OUTPUT BUFFER
Publication Relea Date: April 21, 2005
1. GENERAL DESCRIPTION
The WMS713x is a 32 non-volatile linear digital potentiometers available in 10KΩ, 50KΩ and 100KΩresistance values. The WMS7130/1 can be ud as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications.
The output of each potentiometer is determined by the wiper position, which varies in linearly between V A and V B terminal according to the content stored in the volatile Tap Register (TR) which is programmed through Up/Down (Increment/Decrement) interface. The channel has one non-volatile memory location (NVMEM0) that can be directly written to by urs through the Up/Down interface. Power-on recall is also built in so the content of the NVMEM0 to Tap Register is automatically loaded. The WMS7130/1 devices pin out the resistor wiper directly. The WMS7131 devices feature an output buffer with 3mA minimum drive capability.
All the WMS7130/1 devices are single channel devices offered in 8-pin PDIP, SOIC and MSOP packages. The WMS7130/1 devices operate over a wide operating voltage ranging from 2.7V to 5.5V.
2. FEATURES
•Drop-in replacements for many popular parts
•Available output buffer for WMS7131 devices
•Single linear-taper channel
永远不放手
• 32 taps
•10K, 50K and 100K end-to end resistance
•V SS to V DD terminal voltages
•Non-volatile storage of wiper positions with power-on recall
•Data storage and potentiometer control through Up/Down (3-wire) interface梁翠萍
山岭造句
•Endurance 100,000 write cycles
•Data retention 100 years
• Package options:
o8-pin PDIP, SOIC or MSOP
•Industrial temperature range: -40° ~ 85°C
•Single supply operation 2.7V to 5.5V
我电脑
Publication Relea Date: April 21, 2005
3. BLOCK DIAGRAM
CS V SS
V DD
V A
V B
V W
INC U/D
FIGURE 1 – WMS7130 BLOCK DIAGRAM (Rheostat Mode)
CS V SS
V DD
V A
V B
V W
INC U/D
FIGURE 2 – WMS7131 BLOCK DIAGRAM (Divider Mode)
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION (2)
2. FEATURES (2)
3. BLOCK DIAGRAM (3)
4. TABLE OF CONTENTS (4)
5. PIN CONFIGURATION (5)
6. PIN DESCRIPTION (6)
7. FUNCTIONAL DESCRIPTION (7)
7.1. Potentiometer and Rheostat Modes (7)
7.1.1. Rheostat Configuration (7)
7.1.2. Potentiometer Configuration (7)
7.2. Non-Volatile Memory (NVMEM) (7)
7.3. Serial Data Interface (8)
7.4. Operation Overview (8)
8. TIMING DIAGRAMS (9)
9. ABSOLUTE MAXIMUM RATINGS (11)
杨么
10. ELECTRICAL CHARACTERISTICS (12)
10.1 Test Circuits (14)
11. TYPICAL APPLICATION CIRCUITS (15)
11.1. Layout Considerations (17)
两个王一个木>肌肤之钥12. PACKAGE DRAWINGS AND DIMENSIONS (18)
13. ORDERING INFORMATION (21)
14. VERSION HISTORY (22)
中英文简历
5. PIN CONFIGURATION
Publication Relea Date: April 21, 2005
6. PIN DESCRIPTION
TABLE 1 – PIN DESCRIPTION
