Status Register
Note 1: e the "Table 2. Protected Area Sizes".
bit7bit6bit5bit4bit3bit2bit1bit0
SRWD (status register write protect)
QE (Quad Enable)
BP3 (level of protected block)BP2 (level of protected block)BP1 (level of protected block)BP0 (level of
protected block)
WEL (write enable latch)WIP (write in
progress bit)1=status
register write disable
1=Quad
Enable
0=not Quad
Enable
(note 1)(note 1)(note 1)(note 1)7的分解与组成
1=write enable 0=not write enable 1=write operation 0=not in write operation Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile
bit volatile bit
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volatile bit
Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/era/write status register progress. When WIP bit ts to 1, which means the device is busy in program/era/write status register progress. When WIP bit ts to 0, which means the device is not in progress of program/era/write status register cycle.准则是什么意思
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is t to internal write enable latch. When WEL bit ts to 1, which means the internal write enable latch is t, the device can accept program/era/write status register instruction. When WEL bit ts to 0, which means no internal write enable latch; the device will not accept program/era/write status register instruction. The program/era command will be ignored if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both t to 0 and available for next program/era/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs to be confirmed as 0.
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BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in "Table 2. Protected Area Sizes") of the device to against the program/era instruction without hardware protection mode being t. T o write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Th
o bits define the protected area of the memory to against Page Program (PP), Sector Era (SE), Block Era (BE/BE32K) and Chip Era (CE) instructions (only if Block Protect bits (BP3:BP0) t to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default, which is un-protected.
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#, RESET#/HOLD# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET#/HOLD# are disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET/HOLD will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD ts to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0".细细的红线
Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured after the CR bit is t.
TB bit
The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is ud to configure the Block Protect area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which means Top area protect. When it is t as “1”, the protect area will change to Bottom area of the memory device. To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.
L/H switch bit
The Low Power / High Performance bit is a volatile bit. Ur can change the value of L/H switch bit to keep Ultra Low Power mode or High Performance mode. Plea check Ordering Information for the L/H Switch default support.
Configuration Register - 1
bit7bit6bit5bit4bit3bit2bit1bit0
Rerved
DC
(Dummy
Cycle)
Rerved Rerved
TB
(top/bottom
lected)
Rerved Rerved Rerved
x 2READ/
4READ
Dummy
Cycle
x x
0=Top area
protect
1=Bottom
area protect
(Default=0)
x x x
x Volatile bit x x OTP x x x Configuration Register - 2
bit7bit6bit5bit4bit3bit2bit1bit0 Rerved Rerved Rerved Rerved Rerved Rerved L/H Switch Rerved
x x x x x x 0 = Ultra Low power mode
1 = High performance
mode
x
x x x x x x Volatile bit x
一箭穿心打一字谜DC Numbers of Dummy
Cycles
2READ 0 (default)4
18
4READ 0 (default)6
110
Dummy Cycle Table
10-9. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before nding WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to t the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can t or ret the Quad enable (QE) bit and t or ret the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
The quence of issuing WRSR instruction is: CS# goes low→ nding WRSR instruction code→ Status Register data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits, 16 bits or 24 bits data boundary; otherwi, the instruction will be rejected and not executed. The lf-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checke
d during the Write Status Register cycle is in progress. The WIP ts 1 during the tW timing, and ts 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is ret. Plea note that there is another parameter, "Write Status Register cycle time for Mode Changing Switching (tWMS)", which is only for the lf-timed of Mode Switching (changing L/H switch bit). For more detail plea check "Table 17. AC Characteristics".
Table 7. Protection Modes
Note:
1.As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table
2. Protected Area Sizes".
Mode
Status register condition WP# and SRWD bit status Memory Software protection
mode (SPM)
Status register can be written in (WEL bit is t to "1") and
楚些the SRWD, BP0-BP3bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1
The protected area
cannot
雁的诗句be program or era.Hardware protection
mode (HPM)
The SRWD, BP0-BP3 of status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or era.
Figure 15. WRSR flow
