Frequency Multiplier and Zero Delay Buffer
CY2302
Features
•90ps typical jitter OUT2•200ps typical jitter OUT1
•65ps typical output-to-output skew •90ps typical propagation delay •Voltage range: 3.3V±5%, or 5V±10%•Output frequency range: 5MHz-133MHz •Two outputs
•Configuration options allow various multiplications of the reference frequency—refer to Table 1 to determine the specific option which meets your multiplication needs
•Available in 8-pin SOIC package
Table 1.Configuration Options FBIN FS0FS1OUT1OUT2OUT100 2 X REF REF OUT110 4 X REF 2 X REF OUT101REF REF/2OUT1118 X REF 4 X REF OUT200 4 X REF 2 X REF OUT2108 X REF 4 X REF OUT201 2 X REF REF OUT2
1
1
16 X REF
8 X REF
Block Diagram
Pin Configuration
÷Q
FS0FS1
Reference FBIN
Pha Detector Charge Pump
Loop Filter
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÷2
Output Buffer
OUT1
OUT2
Output Buffer
External feedback connection to OUT1 or OUT2, not both
Input
IN OUT2VDD OUT1FS1
8765
FBIN IN GND
FS0
1234
SOIC
Overview
The CY2302 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature. This is explained further in the ctions of this data
sheet titled “How to Implement Zero Delay,” and “Inrting Other Devices in Feedback Path.”
The CY2302 is a pin-compatible upgrade of the Cypress W42C70-01. The CY2302 address some application dependent problems experienced by urs of the older device.
Pin Definitions
Pin Name Pin No.Pin Type Pin Description
IN 2I Reference Input: The output signals will be synchronized to this signal.
FBIN
1
I
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure proper functionality. If the trace between FBIN and the output pin being ud for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the REF signal input (IN).OUT16O Output 1: The frequency of the signal provided by this pin is determined by the feedback signal connected to FBIN, and the FS0:1 inputs (e Table 1).
OUT28O Output 2: The frequency of the signal provided by this pin is one-half of the frequency of OUT1. See Table 1.
VDD
7
P
Power Connections: Connect to 3.3V or 5V. This pin should be bypasd with a 0.1-µF decoupling capacitor. U ferrite beads to help reduce noi for optimal jitter perfor-mance.
GND 3P Ground Connection: Connect all grounds to the common system ground plane.FS0:1
4, 5
I
Function Select Inputs: Tie to V DD (HIGH, 1) or GND (LOW, 0) as desired per Table 1.
C8
G
Ferrite Bead
Power Supply Connection
V+
G
C A
G
FS1
FS0
GND IN
FBIN 10 µF
0.01
撑组词µF 12
点心的英文3
4
8765
22Ω
22Ω
G
C9 = 0.1 µF OUTPUT 1
OUTPUT 2
OUT 2
V DD
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OUT 1
Figure 1. Schematic/Suggested Layout
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How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are ud becau a designer wants to provide multiple copies of a clock signal in pha with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below.
External feedback is the trait that allows for this compensation. The PLL on the ZDB will cau the feedback signal to be in pha with the reference signal. When laying out the board, match the trace lengths between the output being ud for feedback and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede the input signal, this may also be implemented by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked.
Inrting Other Devices in Feedback Path Another nice feature available due to the external feedback is the ability to synchronize signals to the signal coming from some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) that is p
ut into the feedback path.
Referring to Figure2, if the traces between the ASIC/Buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device will be driven HIGH at the same time the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay from the ZDB output to the ASIC/Buffer output must be accounted for.
Pha Alignment
In cas where OUT1 (i.e., the higher frequency output) is connected to FBIN input pin the output OUT2 rising edges may be either 0 or 180° pha aligned to the IN input waveform (as t randomly when the input and/or power is supplied). If OUT2 is desired to be rising-edge aligned to the IN input’s rising edge, then connect the OUT2 (i.e., the lowest frequency output) to the FBIN pin. This t-up provides a consistent input-output pha relationship.
Figure 2. Six Output Buffer in the Feedback Path
Absolute Maximum Ratings
Stress greater than tho listed in this table may cau permanent damage to the device. The reprent a stress rating only. Operation of the device at the or any other condi-tions above tho specified in the operating ctions of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Parameter Description Rating Unit
V DD, V IN Voltage on Any Pin with Respect to GND–0.5 to +7.0V
T STG Storage Temperature–65 to +150°C
T A Operating Temperature0 to +70°C
T B Ambient Temperature under Bias–55 to +125°C
P D Power Dissipation0.5W
DC Electrical Characteristics: T A = 0°C to 70°C or –40° to 85°C, V DD = 3.3V ±5%
Parameter Description Test Condition Min.Typ.Max.Unit I DD Supply Current Unloaded, 100 MHz—1735mA V IL Input Low Voltage——0.8V V IH Input High Voltage 2.0—V V OL Output Low Voltage I OL = 12 mA ——0.4V V OH Output High Voltage I OH = -12 mA 2.4——V I IL Input Low Current V IN = 0V–40—5µA I IH Input High Current V IN = V DD——5µA
DC Electrical Characteristics: T A = 0°C to 70°C or –40° to 85°C, V DD = 5V ±10%
Parameter Description Test Condition Min.Typ.Max.Unit I DD Supply Current Unloaded, 100 MHz—3750mA V IL Input Low Voltage——0.8V V IH Input High Voltage 2.0—V V OL Output Low Voltage I OL = 12 mA ——0.4V V OH Output High Voltage I OH = -12 mA 2.4—V I IL Input Low Current V IN = 0V–80—5µA I IH Input High Current V IN = V DD—5µA
Notes:
1.Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).
2.Longer input ri and fall time will degrade skew and jitter performance.
3.All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
4.Skew is measured at 1.4V on rising edges.
5.Duty cycle is measured at 1.4V.
6.33 MHz reference input suddenly stopped (0 MHz). Number of cycles provided prior to output falling to <16 MHz.
7.Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst ca.
敢于创新AC Electrical Characteristics: T A = 0°C to +70°C or –40° to 85°C, V DD = 3.3V ±5%[3]
Parameter Description Test Condition
Min.Typ.Max.Unit f IN Input Frequency [1]5—133MHz f OUT Output Frequency OUT1 15-pF load 10—
133MHz t R Output Ri Time 0.8V to 2.0V, 15-pF load —— 3.5ns t F Output Fall Time 2.0V to 0.8V, 15-pF load
—— 2.5ns t ICLKR Input Clock Ri Time [2]
——10ns t ICLKF Input Clock Fall Time [2]—
—10ns t D Duty Cycle 15-pF load [5]
405060%t LOCK PLL Lock Time Power supply stable —— 1.0ms t JC Jitter, Cycle-to-Cycle OUT1, f OUT >30 MHz —200300ps OUT2, f OUT >30 MHz —90300ps t DC Die Out Time [6]100——Clock Cycles
t SKEW Output-output Skew [4]—65250ps t PD
Propagation Delay [4]
–350
雪佛兰斯帕可90
350
ps
AC Electrical Characteristics: T A = 0°C to +70°C or –40° to 85°C, V DD = 5.0V ±10%[3]
Parameter Description Test Condition
Min.Typ.
Max.Unit f IN Input Frequency [1]5133MHz f OUT Output Frequency OUT1 15-pF load 10—133MHz t R Output Ri Time 0.8V to 2.0V, 15-pF load —— 2.5ns t F Output Fall Time 2.0V to 0.8V, 15-pF load
—— 1.5ns t ICLKR Input Clock Ri Time [2]——10ns t ICLKF Input Clock Fall Time [2]——10ns t D Duty Cycle 15-pF load [5, 7]405060%t LOCK PLL Lock Time Power supply stable —— 1.0ms t JC Jitter, Cycle-to-Cycle OUT1, f OUT >30 MHz —200300ps OUT2, f OUT >30 MHz —90300ps t DC Die out time [6]
100——clock cycles t SKEW Output-output Skew [4]—65250ps t PD
Propagation Delay [4]
–350
90350
ps
Ordering Information
Ordering Code Package Type Temperature Grade
CY2302SC-18 pin SOIC Commercial
CY2302SC-1T8 pin SOIC - Tape and Reel Commercial
雾漫小东江CY2302SI-18 pin SOIC Industrial
CY2302SI-1T8 pin SOIC - Tape and Reel Industrial
Lead-free
CY2302SXC-18 pin SOIC Commercial
CY2302SXC-1T8 pin SOIC - Tape and Reel Commercial
CY2302SXI-18 pin SOIC Industrial
CY2302SXI-1T8 pin SOIC - Tape and Reel Industrial
Package Diagram
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Document #: 38-07154 Rev. *A Page 6 of 7
