UCC2810UCC3810
FEATURES
•Single Oscillator Synchronizes Two PWMs
•150 A Startup Supply Current •2mA Operating Supply Current •Operation to 1MHz •Internal Soft Start •Full-Cycle Fault Restart
•Internal Leading Edge Blanking of the Current Sen Signal •1 Amp Totem Pole Outputs
•75ns Typical Respon from Current Sen to Output
•1.5% Tolerance Voltage Reference
DESCRIPTION
玉米沙拉
The UCC3810is a high-speed BiCMOS integrated circuit which imple-ments two synchronized pul width modulators for u in off-line and DC-to-DC power supplies.
The UCC3810provides perfect synchronization between two PWMs by us-ing the same oscillator.The oscillator’s sawtooth waveform can be ud for slope compensation if required.
顽皮的杜鹃
Using a toggle flip flop to alternate between modulators,the UCC3810en-sures that one PWM will not slave,interfere,or otherwi affect the other PWM.This toggle flip flop also ensures that each PWM will be limited to 50%maximum duty cycle,insuring adequate off-time to ret magnetic el-ements.
This IC contains many of the same elements of the UC3842current mode controller family,combined with the enhancements of the UCC3802.This minimizes power supply parts count.Enhancements include leading edge blanking of the current n signals,full cycle fault restart,CMOS output drivers,and outputs which remain low even when the supply voltage is re-moved.
Dual Channel Synchronized Current Mode PWM
BLOCK DIAGRAM
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS Array V CC Voltage (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V
V CC Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
OUT1, OUT2 Current, Peak, 5% Duty Cycle. . . . . . . . . . . .±1A
OUT1, OUT2 Energy (Capacitive Load). . . . . . . . . . . . . .20µJ
Analog Inputs (FB1, FB2, CS1, CS2, SYNC). . . .–0.3V to 6.3V
Operating Junction Temperature. . . . . . . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 conds). . . . . . . . . .300°C
Note 1: All voltages are with respect to GND. All currents are
positive into the specified terminals.
Note 2: Consult Unitrode Integrated Circuits Product & Appli-
cations Handbook for information regarding thermal
specifications and limitations of packages.
Note 3:In normal operation, V CC is powered through a current
limiting resistor. Absolute maximum of 11V applies
when driven from a low impedance such that the V CC
current does not exceed 20mA.
ELECTRICAL CHARACTERISTICS:Unless otherwi stated, the specifications apply for –55°C≤T A≤125°C for UCC1810; –40°C≤T A≤85°C for UCC2810; 0°C≤T A≤70°C for UCC3810; V CC= 10V (Note 4); R T= 150k; C T= 120pF;
No Load; T A= T J. All parameters are the same for both channels.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Reference Section
Output Voltage T J= 25°C 4.925 5.000 5.075V Load Regulation0mA < I REF< 5mA525mV Line Re
gulation UVLO Stop Threshold Voltage +0.5V < V CC< Shunt
12mV
Voltage
Output Voltage Full temperature range, 0mA < I REF< 5mA 4.85 5.00 5.10V Output Noi Voltage10Hz < f < 10kHz, T J= +25°C (Note 10)235µV Long Term Stability T A= +125°C, 1000 Hours (Note 10)5mV Output Short Circuit Current–8–25mA Oscillator Section
Oscillator Frequency R T= 30k, C T= 120pF (Note 5)8409401040kHz Oscillator Frequency R T= 150k, C T= 120pF (Note 5)200220240kHz Temperature Stability(Note 10) 2.5% Peak Voltage 2.5V Valley Voltage0.05V Peak-to-Peak Amplitude 2.25 2.45 2.65V SYNC Threshold0.80 1.65 2.2V SYNC Input Current SYNC = 5V30µA Error Amplifier Section
FB Input Voltage COMP = 2.5V 2.44 2.50 2.56V FB Input Bias Current±1µA Open Loop Voltage Gain6073dB Unity Gain Bandwidth(Note 10)2MHz COMP Sink Current FB = 2.7V, COMP = 1V0.3 1.4 3.5mA COMP Source Current FB = 1.8V, COMP = 4V–0.2–0.5–0.8mA Minimum Duty Cycle COMP = 0V0% COMP Soft Start Ri Time FB = 1.8V, Ri from 0.5V to REF–1.5V5ms
ELECTRICAL CHARACTERISTICS:Unless otherwi stated, the specifications apply for –55°C ≤T A ≤125°C for
UCC1810; –40°C ≤T A ≤85°C for UCC2810; 0°C ≤T A ≤70°C for UCC3810; V CC = 10V (Note 4); R T = 150k; C T = 120pF;No Load; T A = T J . All parameters are the same for both channels.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Current Sen Section Gain
(Note 6)
1.20 1.55 1.80V/V Maximum Input Signal COMP = 5V (Note 7)
0.9
1.0
1.1V CS Input Bias Current ±200
nA CS to OUT Propagation Delay CS steps from 0V to 1.2V, COMP = 2.5V 75ns CS Blank Time
(Note 8)
55ns CS Overcurrent Threshold 1.35 1.55 1.85V COMP to CS Offt CS = 0V
0.65
0.95
1.4
文化环境
V表示团结的名言
PWM Section
Maximum Duty Cycle R T = 150k, C T = 120pF (Note 10)454950%Maximum Duty Cycle R T = 30k, C T = 120pF (Note 10)40
4548
%Minimum On Time CS =1.2V, COMP = 5V
130
ns
Output Section OUT Low Level
I OUT = 20mA 0.120.42V I OUT = 200mA
0.48 1.10V I OUT = 20mA, V CC = 0V
0.7 1.20V OUT High Level (V CC - OUT)I OUT = –20mA 0.150.42V I OUT = –200mA 1.20 2.30V OUT Ri Time C OUT = 1nF 2050ns OUT Fall Time
C OUT = 1nF
30
60
ns
Undervoltage Lockout Section Start Threshold 9.911.313.2V Stop Threshold 7.58.39.5V Start to Stop Hysteresis 1.7 3.0 4.7V ENABLE2 Input Bias Current ENABLE2 = 0V
–20–35–55µA ENABLE2 Input Threshold Voltage 0.80
1.53
2.00
V
Overall Section Startup Current
V CC < Start Threshold Voltage 0.150.25mA Operating Supply Current,Outputs Off
V CC = 10V, FB = 2.75V
2.0
3.0mA Operating Supply Current,Outputs On
V CC = 10V, FB = 0V, CS = 0V, R T = 150k 3.2 5.1mA Operating Supply Current,Outputs On
V CC = 10V, FB = 0V, CS = 0V, R T = 30k 8.514.5mA V CC Internal Zener Voltage I CC = 10mA (Note 9)
11.012.914.0
V V CC Internal Zener Voltage Minus Start Threshold Voltage
0.4
1.2
V
Note 4: Adjust V CC above the start threshold before tting at 10V.Note 5: Oscillator frequency is twice the output frequency.F RT CT
OSC ≈
×4Note 6: Current Sen Gain A is defined by:
A VCOMP
VCS
VCS V =
≤≤∆∆008..
Note 7: Parameter measured at trip point of latch with FB = 0V.
Note 8: CS Blank Time is measured as the difference between the minimum non-zero on-time and the CS to OUT delay.Note 9: Start Threshold Voltage and V CC Internal Zener Voltage track each other.Note 10: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
COMP1,COMP2:The low impedance outputs of the er-ror amplifiers.
CS1,CS2:The current n inputs to the PWM com-parators.The inputs have leading edge blanking.For most applications,no input filtering is required.Leading edge blanking disconnects the CS inputs from all inter-nal circuits for the first55ns of each PWM cycle.When ud with very slow diodes or in other applications where the current n signal is unusually noisy,a small current n RC filter may be required.
CT:The timing capacitor of the oscillator.Recom-mended values of C T are between100pF and1nF.Con-nect the timing capacitor directly across C T and GND. ENABLE2:A logic input which disables PWM2when low.This input has no effect on PWM1.This input is in-ternally pulled high.In most applications it can be left floating.In unusually noisy applications,the input should be bypasd with a1nF ceramic capacitor.This input has TTL compatible thresholds.
FB1,FB2:The high impedance inverting inputs of the error amplifiers.
GND:To parate noi from the critical control circuits, this part has two different ground connections:GND and PWRGND.GND and PWRGND must be electrically connected together.However,u care to avoid cou-pling noi into GND.
OUT1,OUT2:The high current push-pull outputs of the PWM are intended to drive power MOSFET g
ates through a small resistor.This resistor acts as both a cur-rent limiting resistor and as a damping impedance to minimize ringing and overshoot.PWRGND:To parate noi from the critical control circuits,this part has two different ground connections: GND and PWRGND.GND and PWRGND must be elec-trically connected together.
REF:The output of the5V reference.Bypass REF to GND with a ceramic capacitor≥0.01µF for best perfor-mance.
RT:The oscillator charging current is t by the value of the resistor connected from R T to GND.This pin is regu-lated to1V,but the actual charging current is10V/R T. Recommended values of R T are between10k and470k. For a given frequency,higher timing resistors give higher maximum duty cycle and slightly lower overall power consumption.Supply current decreas with in-cread R T by the relationship:
∆ICC
V
RT
三沙
=
11
For more information,e the detailed oscillator block diagram.
SYNC:This logic input can be ud to synchronize the oscillator to a free running oscillator in another part.This pin is edge triggered with TTL thresholds,and requires at least a10ns wide pul.If unud,this pin can be grounded, open circuited, or connected to REF.
VCC:The power input to the IC.This pin supplies cur-rent to all functions including the high current output stages and the precision reference.Therefore,it is criti-cal that V CC be directly bypasd to PWRGND with an 0.1µF ceramic capacitor.
Leading Edge Blanking and Current Sen
Figure1.shows how an external power stage is con-nected to the UCC3810.The gate of an external power N-channel MOSFET is connected to OUT through a small current limiting resistor.For most applications,a 10Ωresistor is adequate to limit peak current and also practical at damping resonances between the gate driver and the MOSFET input reactance.Long gate lead length increas
es gate capacitance and mandates a higher -ries gate resistor to damp the RLC tank formed by the lead,the MOSFET input reactance,and the UCC3810 driver output resistance.The UCC3810features internal leading edge blanking of the current n signal on both current n inputs. The blank time starts when OUT ris and continues for 55ns.During that55ns period,the signal on CS is ig-nored.For most PWM applications,this means that the CS input can be connected to the current n resistor as shown above.However,high speed grounding prac-tices and short lead lengths are still required for good performance.
APPLICATION INFORMATION
APPLICATION INFORMATION (cont.)
感烟探测器
Oscillator
The UCC3810oscillator generates a sawtooth wave at CT.The sawtooth ri time is t by the resistor from RT to GND.Since RT is biad at 1V,the current in RT is 1V/RT.The actual charging current is 10times higher.The fall time is t by an internal transistor on-resistance of approximately 100Ω.During the fall time,all outputs are off and the maximum duty cycle is reduced below 50%.Larger timing capacitors increa the discharge time and reduce frequency.However,the percentage
经典老回民菜maximum duty cycle is only a function of the timing resis-tor RT and the internal 100Ωdischarge resistance.Error Amp Output Stage
The UCC3810error amplifiers are operational amplifiers with low output resistance and high input resistance.The output stage of one error amplifier is shown above.This output stage allows the error amplifier output to swing clo to GND and as high as one diode drop below 5V
with little loss in amplifier performance.
精品课件
