201-0000-056 Rev. 1.5, 3/17/2010
1
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CH7301C
CH7301C DVI Transmitter Device
Features
•DVI Transmitter up to 165M pixels/cond •DVI low jitter PLL •DVI hot plug detection
•Supporting graphics resolutions up to 1600x1200 pixels and 1920x1200 reduced blanking •Providing RGB output •DAC connection detection •Programmable power management •Fully programmable through rial port •Complete Windows and DOS driver support •Low voltage interface support to graphics device •Three 10-bit video DAC outputs •Offered in a 64-pin LQFP package
General Description
The CH7301C is a display controller device which accepts a digital graphics input signal, and encodes and transmits data through a DVI or DFP (Digital flat panel). The device accepts data over one 12-bit wide variable voltage data port which supports different data formats including RGB and YCrCb.
The DVI processor includes a low jitter PLL for generation of the high frequency rialized clock, and all circuitry required to encode, rialize and transmit data. The CH7301C comes in versions able to drive a DFP display at a pixel rate of up to 165MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device. See Figure 1 for the functional block diagram of the CH7301C.
Color space conversion from YCrCb to RGB is supported in both DVI and VGA bypass modes.
Figure 1. Functional Block Diagram
CHRONTEL CH7301C 1. P IN D ESCRIPTIONS扇子功
1.1 Package Diagram
Figure 2. 64-Pin LQFP
2201-0000-056 Rev. 1.5, 3/17/2010
CHRONTEL CH7301C 1.2 Pin Description
Table 1. Pin Description
64-Pin
LQFP
# Pins Type Symbol Description
21In DE Data Enable
This pin accepts a data enable signal which is high when active video
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data is input to the device, and low all other times. The levels are 0 to
DVDDV, and the VREF signal is ud as the threshold level. This
input is ud by the DVI.
31In VREF Reference Voltage Input
The VREF pin inputs a reference voltage of DVDDV / 2. The signal
is derived externally through a resistor divider and decoupling
capacitor, and will be ud as a reference level for data, sync, data
enable and clock inputs.
41In/Out H Horizontal Sync Input / Output
This pin receives / nds out horizontal sync input from / output to the
graphics controller.
51In/Out V Vertical Sync Input / Output
日常生活小妙招This pin receives / nds vertical sync input from / output to the
graphics controller.
71In/Out GPIO[1] /
HPINT General Purpo Input - Output[1] /
DVI Detect Output (Open drain or internal weak pull-up)
This pin provides a general purpo I/O controlled via the rial port bus. The internal pull-up will be to the DVDD supply.
When the GPIO[1] pin is configured as an input, this pin can be ud to output the DVI detect signal (pulls low when a termination change has been detected on the HPDET input). This is an open drain output. The output is relead through rial port control.
81In/Out GPIO[0]General Purpo Input - Output[0]
(Open drain or internal weak pull-up)
This pin provides a general purpo I/O controlled via the rial port. 91In Hot Plug Detect (internal pull-down)
This input pin determines whether the DVI is connected to a DVI
monitor. When terminated, the monitor is required to apply a voltage
greater than 2.4 volts. Changes on the status of this pin will be relayed
to the graphics controller via the HPINT or GPIO[1]/HPINT pin
pulling low.
When the HPDET is pulled low, the DVI output driver will be shut
down.
101In AS Address Select (Internal pull-up)
This pin determines the rial port address of the device
(1,1,1,0,1,AS*,AS).
131In RESET*Ret * Input (Internal pull-up)
When this pin is low, the device is held in the power-on ret
condition. When this pin is high, ret is controlled through the rial
port register.
141In/Out SPD Serial Port Data Input / Output
This pin functions as the rial data pin of the rial port interface, andyy语音聊天
us the DVDDV supply.
201-0000-056 Rev. 1.5, 3/17/20103
CHRONTEL
CH7301C
4201-0000-056 Rev. 1.5, 3/17/2010
64-Pin LQFP
# Pins Type Symbol
Description
15
1
In
SPC
Serial Port Clock Input
顾客参与This pin functions as the clock pin of the rial port interface, and us the DVDDV supply.191In VSWING
DVI Swing Control
This pin ts the swing level of the DVI outputs. A 2.4K ohm resistor should be connected between this pin and TGND using short and wide traces.
22, 212Out TDC0,TDC0*
DVI Data Channel 0 Outputs
The pins provide the DVI differential outputs for data channel 0(blue).
25, 242Out TDC1,TDC1*
DVI Data Channel 1 Outputs
The pins provide the DVI differential outputs for data channel 1(green).
28, 272Out TDC2,TDC2*
DVI Data Channel 2 Outputs
The pins provide the DVI differential outputs for data channel 2(red).
30, 312Out TLC,TLC*
DVI Clock Outputs
The pins provide the differential clock output for the DVI interface corresponding to data on the TDC[0:2] outputs.
351In ISET
Current Set Resistor Input
This pin ts the DAC current. A 140 ohm resistor should be connected between this pin and GND (DAC ground) using short and wide traces.
361In TEST TEST Input
This pin is ud for factory test and should be tied to GND or left N/C.
37
1
Out
G
Green Output
This pin will output the Green component of RGB when RGB bypass mode is ud.381Out R
Red Output
This pin will output the Red component of RGB when RGB bypass mode is ud.391Out B
Blue Output
This pin will output the Blue component of RGB when RGB bypass mode is ud.16, 41, 42, 43, 44, 466NC
No Connect
47
1Out VSYNC
Vertical Sync Output
A buffered version of VGA vertical sync can be acquired from this pin.(Refer to Register 21h, DC register)
Table 1. Pin Description
CHRONTEL CH7301C 64-Pin
LQFP
# Pins Type Symbol Description
481Out HSYNC Horizontal Sync Output
A buffered version of VGA horizontal sync can be acquired from this
pin. (Refer to Register 21h, DC register)
50 – 55, 58 – 6312In D[11] -
D[0]
Data[11] through Data[0] Inputs
The pins accept the 12 data inputs from a digital video port of a
graphics controller. The levels are 0 to DVDDV, and the VREF
signal is ud as the threshold level.
57, 562In XCLK,
XCLK*External Clock Inputs
The inputs form a differential clock signal input to the CH7301C for u with the H, V, DE and D[11:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. The output clocks from this pad cell are able to have their polarities reverd under the control of the MCP bit (in register 1Ch).
1, 12, 493Power DVDD Digital Supply Voltage (3.3V)
6, 11, 643Power DGND Digital Ground
451Power DVDDV I/O Supply Voltage (1.1V to 3.3V)
23, 292Power TVDD DVI Transmitter Supply Voltage (3.3V)
20, 26,
32
3Power TGND DVI Transmitter Ground
181Power A VDD PLL Supply Voltage (3.3V)上行宽带
173Power AGND PLL Ground
331Power VDD DAC Supply Voltage (3.3V)
污动漫图片34, 402Power GND DAC Ground
Table 1. Pin Description
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