Spread Aware™, Frequency Multiplier and Zero Delay Buffer
W170-01
Features
•Spread Aware™—designed to work with SSFTG reference signals •Two outputs
•Configuration options allow various multiplication of the reference frequency, refer to Table 1 to determine the specific option which meets your multiplication needs
•Available in 8-pin SOIC package
Key Specifications
Operating Voltage: ...........................3.3V±5% or 5.0V± 10%Operating Range: .......................20 MHz < f OUT1 < 133 MHz Absolute Jitter: .........................................................±500 ps Output to Output Skew: ..............................................250 ps Propagation Delay:...................................................±350 ps Propagation delay is affected by input ri time.
Table 1.Configuration Options
FBIN FS0FS1OUT1OUT2OUT100 2 X REF REF OUT110 4 X REF 2 X REF OUT101REF REF/2OUT1118 X REF 4 X REF OUT200 4 X REF 2 X REF OUT2108 X REF 4 X REF OUT201 2 X REF REF OUT2
1
1
16 X REF
8 X REF
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Block Diagram
Pin Configuration
÷Q
FS0FS1
Reference FBIN
一杯咖啡多少钱
Pha Detector Charge Pump
Loop Filter
VCO
÷2
Output Buffer
OUT1
OUT2此时此刻
Output Buffer
External feedback connection to OUT1 or OUT2, not both
Input
幽幽IN OUT2VDD OUT1FS1
8765
FBIN IN GND
FS0
1234
元器件交易网
Overview
The W170-01 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing max-imum flexibility when implementing the Zero Delay feature. This is explained further in the ctions of this data sheet titled “How to Implement Zero Delay,” and “Inrting Other Devices in Feedback Path.”
The W170-01 is a pin-compatible upgrade of the Cypress W42C70-01. The W170-01 address some application de-pendent problems experienced by urs of the older device. Most importantly, it address the tracking skew problem in-duced by a reference which has Spread Spectrum Timing en-abled on it.Spread Aware
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we de-signed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant a
mount of tracking skew which may cau problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology, plea e the Cypress application note titled, “EMI Suppres-sion T echniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.”
Pin Definitions
Pin Name Pin No.
Pin
Type Pin Description
IN2I Reference Input: The output signals will be synchronized to this signal.
西南政法大学研究生招生简章FBIN1I Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to
ensure proper functionality. If the trace between FBIN and the output pin being ud
for feedback is equal in length to the traces between the outputs and the signal desti-
nations, then the signals received at the destinations will be synchronized to the REF
signal input (IN).
OUT16O Output 1: The frequency of the signal provided by this pin is determined by the feed-
back signal connected to FBIN, and the FS0:1 inputs (e Table 1).
OUT28O Output 2: The frequency of the signal provided by this pin is one-half of the frequency
of OUT1. See T able 1.
VDD7P Power Connections: Connect to 3.3V or 5V. This pin should be bypasd with a
0.1-µF decoupling capacitor. U ferrite beads to help reduce noi for optimal jitter
performance.
GND3P Ground Connection: Connect all grounds to the common system ground plane.
FS0:14, 5I Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per
Table 1.
How to Implement Zero Delay
T ypically, zero delay buffers (ZDBs) are ud becau a de-signer wants to provide multiple copies of a clock signal in pha with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this,layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below.
External feedback is the trait that allows for this compensation.The PLL on the ZDB will cau the feedback signal to be in pha with the reference signal. When laying out the board,match the trace lengths between the output being ud for feed back and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked.
Inrting Other Devices in Feedback Path
Another nice feature available due to the external feedback is the ability to synchronize signals up to the signal coming from
some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path.
Referring to Figure 2, if the traces between the ASIC/Buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device will be driven HIGH at the same time the Reference clock provided to the ZDB goes HIGH.Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for.
Figure 1.Schematic/Suggested Layout
C8
G
Ferrite Bead
Power Supply Connection
V+
G
C A
G
FS1
FS0
GND
IN
FBIN
10 µF
0.01 µF
1
23
4
8
7
6
5
22Ω
22Ω
G
C9 = 0.1 µF
OUTPUT 1
OUTPUT 2
OUT 2
V DD
OUT 1
Reference Signal Feedback Input
ASIC/Buffer
Zero Delay Buffer
A
戳组词Figure 2. 6 Output Buffer in the Feedback Path
Absolute Maximum Ratings
Stress greater than tho listed in this table may cau per-manent damage to the device. The reprent a stress rating only. Operation of the device at the or any other conditions above tho specified in the operating ctions of this specifi-cation is not implied. Maximum conditions for extended peri-ods may affect reliability.
Parameter Description Rating Unit
V DD, V IN Voltage on any pin with respect to GND–0.5 to +7.0V
生物教学反思T STG Storage T emperature –65 to +150°C
T A Operating Temperature0 to +70°C
T B Ambient T emperature under Bias–55 to +125°C
P D Power Dissipation0.5W
DC Electrical Characteristics: T A =0°C to 70°C, V DD = 3.3V ±5%
Parameter Description Test Condition Min Typ Max Unit I DD Supply Current Unloaded, 133 MHz1735mA V IL Input Low Voltage0.8V V IH Input High Voltage 2.0V V OL Output Low Voltage I OL = 8 mA0.4V V OH Output High Voltage I OH = 8 mA 2.4V I IL Input Low Current V IN = 0V5µA I IH Input High Current V IN = V DD5µA
DC Electrical Characteristics: T A =0°C to 70°C, V DD = 5V ±10%
Parameter Description Test Condition Min Typ Max Unit I DD Supply Current Unloaded, 133 MHz3150mA V IL Input Low Voltage0.8V V IH Input High Voltage 2.0V V OL Output Low Voltage I OL = 8 mA0.4V V OH Output High Voltage I OH = 8 mA 2.4V I IL Input Low Current V IN = 0V5µA I IH Input High Current V IN = V DD5µA
Document #: 38-00795
AC Electrical Characteristics: T A = 0°C to +70°C, V DD = 3.3V±5%
Parameter Description
Test Condition Min
Typ
Max
Unit f IN Input Frequency [1]OUT2 = REF MHz f OUT Output Frequency OUT1
20
133MHz t R Output Ri Time 0.8V to 2.0V , 15-pF load 3.5ns t F Output Fall Time 2.0V to 0.8V , 15-pF load
2.5ns t ICLKR Input Clock Ri Time [2]10ns t ICLKF Input Clock Fall Time [2]
10ns t PD FBIN to IN (Reference Input) Skew [3, 4]Note 4300ps t D Duty
Cycle Note屏气凝神的意思
5
40
50
60%t LOCK PLL Lock Time Power supply stable 1.0ms t JC
Jitter, Cycle-to-Cycle
Note 6
200
ps
AC Electrical Characteristics: T A = 0°C to +70°C, V DD = 5V±10%
Parameter Description
Test Condition Min
Typ
Max
Unit f IN Input Frequency [1]OUT2 = REF MHz f OUT Output Frequency OUT1
20
133MHz t R Output Ri Time 0.8V to 2.0V , 15-pF load 3.5ns t F Output Fall Time 2.0V to 0.8V , 15-pF load 2.5ns t ICLKR Input Clock Ri Time [2]10ns t ICLKF Input Clock Fall Time [2]
10ns t PD FBIN to IN (Reference Input) Skew [3, 4]Note 4300ps t D Duty Cycle Note 7, 8
40
50
60%t LOCK PLL Lock Time Power supply stable 1.0ms t JC
Jitter, Cycle-to-Cycle
Note 6
200
ps
Notes:
1.Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).
2.Longer input ri and fall time will degrade skew and jitter performance.
3.All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V .
4.Skew is measured at 1.4V on rising edges.
5.Duty cycle is measured at 1.4V .
6.Jitter is measured on 133-MHz signal at 1.4V.
7.Duty cycle is measured at 1.4V , 120 MHz.
8.Duty cycle at 133 MHz is 35/65 worst ca.
Ordering Information
Ordering Code Option Package Name
Package Type
W170
-01
G
8-pin SOIC (150 mil)
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the u of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any licen under patent or other rights. Cypress Semiconductor does not authorize its product
s for u as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the ur. The inclusion of Cypress Package Diagram
8-Pin Small Outlined Integrated Circuit (SOIC, 150 mil)
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