MIC5841/5842
8-Bit Serial-Input Latched Drivers
Micrel Inc. • 2180 Fortune Drive • San Jo, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
General Description
Using BiCMOS technology, the MIC5841/5842 integrated circuits were fabricated to be ud in a wide variety of peripheral power driver applications. The devices each have an eight-bit CMOS shift register, CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sink Darlington output drivers.
The two devices differ only in maximum voltage ratings. The MIC5842 offers premium performance with a minimum output breakdown voltage rating of 80V (50V
sustaining). The drivers can be operated with a split supply
where the negative supply is down to –20V.
The 500mA outputs, with integral transient-suppression
diodes, are suitable for u with lamps, relays, solenoids and other inductive loads.
The devices have improved speed characteristics. With a 5V logic supply, they will typically operate faster than 5 MHz. With a 12V supply, significantly higher speeds are obtained. The CMOS inputs are compatible with standard CMOS, PMOS, and NMOS logic levels. TTL or DTL circuits may require the u of appropriate pull-up resistors. By using the rial data output, the drivers can be cascaded for interface applications requiring additional drive lines.
The MIC5840 family is available in DIP, PLCC, and SOIC packages. Becau of limitations on package power dissipation, the simultaneous operation of all drivers at maximum rated current might require a reduction in duty cycle. A copper-alloy lead frame provides for maximum package power dissipation.
Features
• 3.3 MHz Minimum Data-Input Rate • CMOS, PMOS, NMOS, TTL Compatible
• Internal Pull-Up/Pull-Down Resistors • Low-Power CMOS Logic and Latches
• High-Voltage Current-Sink Outputs
• Output Transient-Protection Diodes • Single or Split Supply Operation
Ordering Information
Part Number
物种命名Standard Pb-Free Temperature Range
Package MIC5841BN MIC5841YN –40ºC to +85ºC 18-Pin Plastic DIP MIC5841BV MIC5841YV –40ºC to +85ºC 20-Pin PLCC MIC5841BWM MIC5841YWM –40ºC to +85ºC 18-Pin Wide SOIC MIC5842BN MIC5842YN –40ºC to +85ºC 18-Pin Plastic DIP MIC5842BV MIC5842YV –40ºC to +85ºC 20-Pin PLCC MIC5842BWM MIC5842YWM
–40ºC to +85ºC
18-Pin Wide SOIC
Functional Diagram
SERIAL DATA OUT CLK
V S S
V DD
S T R O B E
OUTPUT ENABLE (ACTIVE LOW)
8
7654321
Absolute Maximum Ratings (1,2,3)
At 25°C Free-Air Temperature and V SS ...................0V Output Voltage, V CE (MIC5841)............................. 50V (MIC5842)..............................80V Output Voltage, V CE(SUS) (MIC5841)(1)..................................35V (MIC5842)........................50V Logic Supply Voltage, V DD .......................................15V VDD with Reference to V EE .....................................25V
Emitter Supply Voltage, V EE ...................................–20V Input Voltage Range, V IN ...............–0.3V to V DD + 0.3V Continuous Output Current, I OUT .........................500mA Package Power Dissipation, P D (2)........................1.82W Operating Temperature Range, T A .......–55°C to +85°C Storage Temperature Range, T S ........–65°C to +150°C
宠爱的近义词Electrical Characteristics
At T A = 25°C V DD = 5V, V SS = V EE = 0V (unless otherwi noted)
Limits
Characteristic Symbol Applicable Devices Test Conditions
Min Max Unit V OUT = 50V
50 MIC5841
V OUT = 50V, T A = +70ºC
100 V OUT = 80V
50 Output Leakage Current
I CEX
MIC5842 V OUT = 80V, T A = +70ºC
100 µA
I OUT = 100mA
1.1 I OUT = 200mA
1.3 Collector-Emitter Saturation Voltage
V CE(SAT) Both I OUT = 350mA, V DD = 7.0V
1.6
V MIC5841 I OUT = 350mA, L = 2mH
35
Collector-Emitter Saturation Voltage V CE(SUS)(5)
MIC5842 I OUT = 350mA, L = 2mH
50
V V IN(0) Both
0.8
V DD = 12V 10.5 V DD = 10V 8.5 Input Voltage
V IN(1) Both
V DD = 5.0V(4)
3.5 V V DD = 12V
50 V DD = 10V 50 Input Resistance
R IN Both V DD = 5.0V
50
k Ω All Drivers ON, V DD = 12V
16
All Drivers ON, V DD = 10V 14 IDD (ON) Both All Drivers ON, V DD = 5.0V 8.0 All Drivers OFF, V DD = 12V 2.9 All Drivers OFF, V DD = 10V 2.5 Supply Current
IDD (OFF) Both
All Drivers OFF, V DD = 5.0V
1.6 1.6 MIC5841 V R = 50V
50 Clamp Diode Leakage Current I R MIC5842 V R = 80V
50 µA Clamp Diode Forward Voltage
V F Both I F = 350mA
2.0 V
Electrical Characteristics
At T A = –55°C V DD = 5V, V SS = V EE = 0V (unless otherwi noted)
Limits
Characteristic Symbol Test Conditions Min Max Unit Output Leakage Current
I CEX V OUT = 80V 50 µA I OUT = 100mA 1.3 I OUT = 200mA
1.5 Collector-Emitter Saturation Voltage
V CE(SAT)
孙中山简介
I OUT = 350mA, V DD = 7.0V
1.8 V V IN(0)
0.8 V DD = 12V 10.5 Input Voltage
V IN(1)
V DD = 5.0V
3.5 V V DD = 12V
35 V DD = 10V 35 Input Resistance
R IN V DD = 5.0V
35
k Ω All Drivers ON, V DD = 12V
16
All Drivers ON, V DD = 10V 14 I DD(ON) All Drivers ON, V DD = 5.0V
10 All Drivers OFF, V DD = 12V
3.5 Supply Current
I DD(OFF) All Drivers OFF, V DD = 5.0V
2.0
mA
Electrical Characteristics
At T A = +125°C V DD = 5V, V SS = V EE = 0V (unless otherwi noted)
Limits
Characteristic Symbol Test Conditions Min Max Unit Output Leakage Current
I CEX V OUT = 80V 500 µA I OUT = 100mA 1.3 I OUT = 200mA
1.5 Collector-Emitter Saturation Voltage
V CE(SAT)
I OUT = 350mA, V DD = 7.0V
1.8 V V IN(0)
0.8 V DD = 12V 10.5 Input Voltage
V IN(1)
V DD = 5.0V
3.5 V V DD = 12V
50 V DD = 10V 50 Input Resistance
R IN V DD = 5.0V
50 k Ω All Drivers ON, V DD = 12V
16 All Drivers ON, V DD = 10V 14 I DD(ON) All Drivers ON, V DD = 5.0V 8 All Drivers OFF, V DD = 12V 2.9 Supply Current
I DD(OFF)
All Drivers OFF, V DD = 5.0V
2.1.6 mA MIC5841A V R = 50V
1.6 µA Clamp Diode Leakage Current
I R MIC5842A V R = 80V
100
Notes :
1. For Inductive load applications.
2. Derate at the rate of 18.2mW/°C above TA = 25°C (Plastic DIP)
3. CMOS devices have input-static protection but are susceptible to damage when expod to extremely high static electrical charges.
4. Operation of the devices with standard TTL may require the u of appropriate pull-up resistors to insure an input logic HIGH.
5. Not 100% tested. Guaranteed by design.
Timing Conditions
(TA = 25°C Logic Levels are V DD and V SS ) V DD = 5V A. Minimum Data Active Time Before Clock Pul (Data Set-Up Time)...................................................................... 75 ns B. Minimum Data Active Time After Clock Pul (Data Hold Time) ............................................................................75 ns C. Minimum Data Pul Width ...................................................................................................................................150 ns D. Minimum Clock 150 ns E. Minimum Time Between Clock Activation and Strobe ...........................................................................................300 ns F. Minimum Strobe 100 ns G. Typical Time Between Strobe Activation and 500 ns SERIAL DATA prent at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pul. On succeeding CLOCK puls, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information prent at any register is transferred to its respective latch when the STROBE is high (
rial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypasd (STROBE tied high) will require that the ENABLE input be high during rial data entry. When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latches or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches.
MIC5840 Family Truth Table
Shift Register Contents Latch Contents Output Contents Serial Data Input
Clock Input
I 1铁观音春茶价格
I 2
I 3 … I 8
Serial Data Output
西餐用餐礼仪
Strobe Input
I 1
I 2
I 3 … I 8 Output
Enable
I 1
I 2
I 3
…肉末烧茄子
I 8
汉字字根
伤残鉴定等级H H R1 R2 … R7 R7 L L R1 R2 … R7 R7 X R1 R2 R3 … R8 R8
X X X … X X L R1 R2 R3 … R8
P1 P2 P3 … P8
P8 H P1 P2 P3 … P8 L P1 P2 P3 …P8
X X X … X
H
H H H …
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Prent State R = Previous State
