© 2004 Thorsten Gärtner, Oststeinbek / Germany Filename : PRBS.doc
Page 1
www.thorsten-gaertner.de Version : 1.0a Date : 02.10.04
A PRBS (Pudo Random Binary Sequence) is a binary PN (Pudo-Noi) signal. The quence of binary 1’s and 0’s exhibits certain randomness and autocorrelation properties.
Bit-quences like PRBS are ud for testing transmission lines and transmission equipment becau of their randomness properties.
Simple bit-quences are ud to test the DC compatibility of transmission lines and transmission equipment.
The different types of PRBS and the suggested data-rates for the different PRBS types are described in the ITU-T standards O.150, O.151, O.152 and O.153.
PRBS type Standard Suggested Datarate [kbit/c] Feedback tap
2 9
-1 ITU-T O.150 / O.153 up to 14.4 5th + 9th 2 11 -1 ITU-T O.150 / O.152 / O.153 64, n*64 (n=1..31), 48 to 168 9th + 11th 2 15 -1 ITU-T O.150 / O.151 1544, 2048, 6312, 8448, 32064, 44736 14th + 15th 2 20 -1 ITU-T O.150 / O.151 1544, 6312, 32064, 44736 17th + 20th 2 20 -1 ITU-T O.150 / O.153 up to 72 3rd + 20th
(note 1) 2 23 -1 ITU-T O.150 / O.151 34368, 44736, 139264 18th + 23rd 2 29 -1 ITU-T O.150 27th + 29th 2 31 -1 ITU-T O.150 28th + 31st
Note 1 = an output bit is forced to be a ONE whenever the previous 14 bits are all ZERO.
PRBS bit-pattern are generated in a linear feed-back shift-register. This is a shift-register with a xored-feedback of the output-values of specific flip-flops to the input of the first flip-flop.
Example : PRBS-Generation of the quence 2 9 -1 :
At start time all flip-flops are t to ‘1’.
The PRBS and bit-quence tester consists of two modules :
PRBS and bit-quence generator
PRBS and bit-quence receiver
Both modules are plain VHDL bad without any special units (e.g. RAM-blocks from a FPGA vendor).
The modules are synchronous designs with clock and clock-enable inputs. A control port enables the possibility to lect different PRBS quences or bit pattern (See page 4). The generator is able to transmit quences with lectable error rates from 10-1 to 10-12. It has a transmit single bit error input too.
The receiver has signaling outputs for synchronization state, synchronization loss, bit error and clock error.
Synchronization state :
The output goes to high when :
- in PRBS mode 2*X (X = PRBS shift register length [9..31]) error free bits are received带手机检讨书
- in bit pattern mode 20 error free bits are received
The output goes to low if the error rate exceeds 0.2. To detect this level, the bit errors during the last 128 received bits are memorized. If there are more than 25 errors within the 128 bits, the output goes low. Synchronization loss :
When the synchronization upon the received bit quence is lost, the output goes high for one clock period (plus clock enable).
Bit error :
This output goes high, when the receiver is synchronized and a bit error in the received bit quence is detected. This signaling output has a delay of 128 bit times, becau massive bit errors who caus a synchronization loss must not be reported as bit errors.
Clock error :
This output goes high, when the receiver is synchronized and a clock error (bit slip : bit lost or bit inrted) in the received bit quence is detected.
The clock error functionality is not implemented at the moment.
© 2004 Thorsten Gärtner, Oststeinbek / Germany Filename : PRBS.doc Page 2 www.thorsten-gaertner.de Version : 1.0a Date : 02.10.04
PRBS-Generator-Module
PRBS-Generator : VHDL-Entity
entity PRBS_TX_SER is
port (
CLK : in std_logic; -- synchron clock
RESET : in std_logic; -- asynchron ret
CLK_EN : in std_logic; -- clock enable
PRBS_SET : in std_logic; -- t new PRBS / bit pattern
PRBS_TYPE : in std_logic_vector (3 downto 0); -- type of PRBS / bit pattern
PRBS_INV : in std_logic; -- invert PRBS pattern
ERR_INSERT : in std_logic; -- manual error inrt
ERR_SET : in std_logic; -- t new error typeexcel编号>乔任梁意外死亡
ERR_TYPE : in std_logic_vector (3 downto 0); -- error type
TX_BIT : out std_logic -- tx rial output
);
end PRBS_TX_SER;
© 2004 Thorsten Gärtner, Oststeinbek / Germany Filename : PRBS.doc Page 3 www.thorsten-gaertner.de Version : 1.0a Date : 02.10.04
PRBS-Generator : Interface Description
CLK
Ba clock for the PRBS generator. The whole PRBS logic of the generator works with this clock.
RESET鸡蛋炒什么菜谱大全
Asynchronous ret for the whole internal logic of the PRBS generator.
CLK_EN
Clock enable signal for the PRBS generator.
PRBS_SET (synchronous to CLK)
When PRBS_SET is high the generator reads the values on the inputs PRBS_TYPE and PRBY_INV.
PRBS_TYPE (synchronous to CLK)
Input vector for lection of the PRBS quence or of the bit pattern. This vector is read by the generator when PRBS_SET is high.
PRBS_TYPE vector PRBS quence / bit pattern Note
0 0 0 0 2 ^ 9 -1 DC free
0 0 0 1 2 ^ 11 -1 DC free
0 0 1 0 2 ^ 15 -1 DC free
小孩辅食0 0 1 1 2 ^ 20 -1 DC free
0 1 0 0 2 ^ 20 -1 DC free
0 1 0 1 2 ^ 23 -1 DC free
0 1 1 0 2 ^ 29 -1 DC free
0 1 1 1 2 ^ 31 -1 DC free
1 0 0 0 all ’0’ : "00000000" DC only
1 0 0 1 all ’1’ : "11111111" DC only
1 0 1 0 alternating ’0’ and ’1’ : "01010101" DC free
1 0 1 1 alternating ’00’ and ’11’ : "00110011" DC free
1 1 0 0 one ’0’ and ven ’1’ : "01111111" With DC component
1 1 0 1 one ’1’ and ven ’0’ : "10000000" With DC component
1 1 1 0 two ’0’ and six ’1’ : "01110111" With DC component
1 1 1 1 two ’1’ and six ’0’ : "10001000" With DC component
比较级和最高级的用法
PRBS_INV (synchronous to CLK)
Input signal for lection of the polarity of the PRBS quence. A high signal on this input inverts the PRBS bit quence on TX_BIT. This signal is read by the generator when PRBS_SET is high. The polarity of the bit pattern is not affected by PRBS_INV.
© 2004 Thorsten Gärtner, Oststeinbek / Germany Filename : PRBS.doc Page 4 www.thorsten-gaertner.de Version : 1.0a Date : 02.10.04
ERR_INSERT (synchronous to CLK)
Input signal for inrting an error into the actual generated PRBS bit or pattern bit. A rising edge on this input signal (mentioned with CLK) generated exact one defective bit.
ERR_SET (synchronous to CLK)
When ERR_SET is high the generator reads the value on the input ERR_TYPE.
ERR_TYPE (synchronous to CLK)
Input vector for lection of transmitted error rate (if desired). This vector is read by the generator when ERR_SET is high.
ERR_TYPE vector Transmitted error rate Error distance at 100 Mbit/c
0 0 0 0 0 -
0 0 0 1 10 ^ -1 100 ns
0 0 1 0 10 ^ -2 1 us
0 0 1 1 10 ^ -3 10 us
0 1 0 0 10 ^ -4 100 us
0 1 0 1 10 ^ -5 1 ms
0 1 1 0 10 ^ -6 10 ms
0 1 1 1 10 ^ -7 100 ms
1 0 0 0 10 ^ -8 1 c
1 0 0 1 10 ^ -9 10 c
1 0 1 0 10 ^ -10 100 c
1 0 1 1 10 ^ -11 17 min
棋王阿城1 1 0 0 10 ^ -1
2 167 min = 2,8 h
1 1 0 1 variable : 10^-3 to 10^- 6 (not implemented)
1 1 1 0 variable : 10^-3 to 10^-1
2 (not implemented)
1 1 1 1 variable : 10^-9 to 10^-1
2 (not implemented)
TX_BIT (synchronous to CLK)
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Output of the PRBS generator for the PRBS quence alternatively for the bit pattern.
© 2004 Thorsten Gärtner, Oststeinbek / Germany Filename : PRBS.doc Page 5 www.thorsten-gaertner.de Version : 1.0a Date : 02.10.04
