Application Note
TABLE OF CONTENTS
1. Introduction (3)
2. Conformal Software and DesignWare Support (4)
3. Synthesizable DW Components (4)
4. Non-synthesizable DW Components (7)
5. Non-synthesizable DW Replacement Flow (8)
6. Conformal Built-in DW Models (9)
7. Conformal Modified Verilog DW Models (9)
8. Revisions (11)
1. Introduction
This application note will describe the methods to complete Conformal equivalence checking of designs instantiating Synopsys Verilog or VHDL DesignWare (DW) components.
The quality of DW verification available with Conformal is always at least equal to, and in the vast majority of cas is far superior to what is possible with any other equivalence checking solution. Conformal is able to read in a majority of synthesizable Verilog and VHDL DW components and verify them. However, if the simulation model of an instantiated DW component is non-synthesizable, Conformal cannot read in the Verilog or VHDL model description and build the component in the golden design. No equivalence checker can. This means that without taking additional steps available within Conformal to handle such a DW component, it will be treated as a black box. If a DW component is allowed to be modeled as a black box, the equivalence checking of that particular DW component is skipped, and other complications in completing equivalency checking versus a flattened revid gate netlist can ari. In addition, even though Conformal can read in synthesizable DW components, some of them can lead to Conformal fal non-equivalent points or aborts. The flow described here covers all the scenarios.
It is important to note that while Conformal recommends the additional flow steps to allow equivalence checking of non-synthesizable or problematic DW components only, other equivalence checking solutions employ hidden techniques of DW component replacement for ALL DW equivalence checking. That lowers the quality of verification for ALL designs that contain DW components.
2. Conformal Software and DW Support
恒的作文The Conformal DW flow is supported with the following Conformal software and Synopsys DW versions:
Conformal Software: Conformal 6.1 and later
Synopsys DesignWare: 2004.06 (Verilog and VHDL)
NOTE: Within the majority of Verilog and VHDL DW component descriptions, there are embedded translate_off and translate_on directives that will cau Conformal to unnecessarily black-box contents. To disable the directives so Conformal will build the DW correctly, u the following command before reading in the Verilog or VHDL DW components:
t directive off translate_off translate_on
If the directives need to be ud in other parts of the design, then u the –file option to disable the directives in the Verilog or VHDL DW component files only as follows:
泰勒科学管理理论t directive off translate_off translate_on –file DW*
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3. Synthesizable DW Components
疫情儿童画
The following tables, Table 1 for Verilog and Table 2 for VHDL, shows the DW components that Conformal can read in natively for equivalency checking. However, if a component is listed with an asterisk (*), it means that Conformal comparison will result in non-equivalent points. If tho components listed with an asterisk (*) are ud, it is recommended that the ur follows the Non-synthesizable DW replacement flow in Section 5 for tho particular components, to eliminate the non-equivalent points and maximize functional verification.
DW DW01 DW02 DW03 DW04 DW_8b10b_dec DW01_absval DW02_cos DW03_bictr_dcnto DW04_par_gen DW_8b10b_unbal DW01_add DW02_multp * DW03_bictr_scnto DW04_shad_reg DW_addsub_dx DW01_addsub DW02_prod_sum DW03_cntr_gray * DW04_sync DW_arbiter_dp * DW01_ash DW02_sin DW03_lfsr_dcnto *
DW_arbiter_sp * DW01_binenc DW02_sincos DW03_lfsr_load *
DW_bc_1 * DW01_cmp2 DW02_sum DW03_lfsr_scnto *
DW_bc_10 DW01_cmp6 DW02_tree DW03_lfsr_updn *
DW_bc_2 * DW01_csa DW03_pipe_reg
DW_bc_3 * DW01_dec DW03_reg_s_pl
DW_bc_4 * DW01_decode DW03_shiftreg
DW_bc_5 * DW01_inc DW03_updn_ctr
DW_bc_7 * DW01_incdec
DW_bc_8 DW01_mux_any
DW_bc_9 DW01_prienc
DW_bin2gray DW01_satrnd
DW_cmp_dx DW01_sub
DW_control_force
DW_crc_p *清蒸甲鱼的做法
DW_dpll_sd *
DW_ecc *
500字写人作文DW_fir_q *
DW_gray2bin
DW_iir_dc *
DW_iir_sc *
DW_inc_gray
DW_minmax
DW_mult_dx
DW_obrv_dgen
DW_ram_2r_w_a_dff *
DW_ram_2r_w_a_lat
DW_ram_2r_w_s_lat五笔口诀表
DW_ram_r_w_a_dff *
DW_ram_r_w_a_lat
DW_ram_r_w_s_lat
DW_ram_rw_a_dff *
DW_ram_rw_a_lat
DW_ram_rw_s_lat西瓜爆炸
DW_sqrt
DW_square
DW_Z_control_force
Table 1. Synthesizable Verilog DW Components
