12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with1MS/s
Gilbert Promitzer
Abstract—Bad on a conventional successive approximation ADC architecture a new and faster solution is prented.The input structure of the new solution consists of transmission gates and capacitors only and there is no need for any active element.
A switching circuit is implemented to allow a wider input voltage range of the ADC.Together with a lf-timed comparator the power consumption is noticeably reduced while at the same time the sampling rate is doubled.Smaller input and reference capaci-tances reduce the requirements on the input and reference sources, respectively.Additionally,a widely clock-duty-cycle-independent control logic improves the applicability of the converter cell, especially for systems on chip.Results of measurements confirm the theoretical improvements.
Index Terms—CMOS,low power,SC technique,lf-timed com-parator.
I.I NTRODUCTION
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N EW systems on silicon need more functionality integrated in one chip.Large digital parts and more analog func-tions such as analog to digital converters are integrated on one chip.Interference-innsitive fully differential structures with low power consumption should be ud to avoid crosstalk be-tween the converters and the digital part and to minimize lf-heating effects.More and more applications require converters with higher sampling rates at lower power consumption.To ac-commodate the apparently incompatible properties into one ADC,the well-known structure of a fully differential switched capacitor ADC,working in successive approximation,had to be revid.
Section II gives a short description of the ADC structure ud so far,while Section III explains the new structure.The success of the new concept is confirmed by measured results in Sec-tion IV.
II.C ONVENTIONAL ADC A RCHITECTURE
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The ADC architecture of the fully differential successive ap-proximation switched capacitor ADC which was ud so far consists of two capacitor arrays,two blocking capacitors,a fully differential buffer,a fully differential comparator with offt cancellation,a successive approximation register(SAR),and a control logic[1],[2].Various possible structures to realize the track-and-hold function exist[3],[4].In this solution,the whole capacitor array is ud as a track-and-hold stage and a
s a DAC (Maindac)to perform the successive approximation.To increa the resolution and to avoid a large capacitor array another DAC
Manuscript received November20,2000;revid January22,2001.
The author is with Austria Mikro Systeme Int.AG,A-8141Unterpremstätten, Austria(e-mail:gilbert.)
Publisher Item Identifier S
0018-9200(01)04517-6.Fig.1.Conventional ADC
architecture.
Fig.2.Timing of the conventional ADC.
(Subdac)is ud,which interpolates the least significant bit of the capacitive Maindac and may be either resistive or capacitive. Fig.1shows the block diagram of
an
–bit Maindac and
an
Fig.3.Input voltages of the comparator.
of the critical output signals of the two Maindacs,which is re-duced by the large blocking capacitors.The additional capac-itors increa the input and reference capacitance of the ADC. For a12-bit converter,the input and reference capacitance is four times larger than that for a10-bit converter.In most appli-cations,an on-chip buffer is ud to provide the input signal to the ADC,but with such a large input capacitance,it is very hard to achieve more than250kHz with12-bit accuracy in an inte-grated system.
During the tracking pha,the offt cancellation is per-formed.In this pha,the common-mode input voltage of the comparator depends on the voltage VCM,which is derived from the reference voltage.During the successive approxima-tion pha the common mode input voltage of the compar
ator depends on the common mode voltage of the input signal. So the operating point of the comparator during the offt cancellation is different to that at a critical decision.This difference can be up to one quarter of the supply voltage and might cau a gain error or INL error due to an insufficient common-mode rejection ratio(CMRR)of the comparator. Fig.3illustrates the variation of the operating point for two different input voltages in single ended mode.In both cas
幼儿园劳动教育the Fig.4.New ADC
architecture.
Fig.5.Timing of the new ADC architecture.
input VINB is connected to the VCM voltage.In Fig.3,the conversion of the maximum negative voltage difference at the input,which corresponds to the digital output code0,is shown on the top whereas the maximum positive voltage difference, which is converted to the digital output code1023,is shown on the bottom.
Another problem is the reduction of the input voltage swing at the comparator input due to the voltag
e divider built by the blocking capacitors.The swing is reduced to one quarter of the supply voltage,which decreas the signal to noi ratio of the whole converter.
The cond part of the conversion is the successive approx-imation pha,which
takes
Fig.6.Input voltages of the comparator.
During the tracking pha,the sample switch S1and the input switches S2are on.Both capacitor arrays are charged to (VIN–VINB)/2,even in single-ended mode.In Fig.6,the input voltagesofthecomparatorareshownforthesametupasinFig.3. During the whole conversion,no overshoots or undershoots are possible,even without the blocking capacitors.This elimi-nates the need for blocking capacitors and increas the input voltage swing of the comparator to half of the supply,which increas the signal to noi ratio of the whole converter by2. Becau of the ries connection of the two capacitor arrays and the nonexisting blocking capacitors,it was possible to improve the resolution from10to12bit without rising the capacitive load.This makes the implementation of an on-chip input buffer easier and allows higher frequencies for the input signal.
An additional advantage is a more simplified implementation of a power-down option,becau the only active component re-maining has enough time to perform the power up.
B.Enhanced Range of the Input Voltage
For decoupling the comparator stage from the input voltage during the tracking pha,some additional switches are inrted, as shown in Fig.7and described in
[6].Fig.7.Decoupling of the comparator
stage.
Fig.8.Self-timed
comparator.
Fig.9.Timing of lf-timed comparator.
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In the tracking pha,the switches S4are off and the switches S1and S5are on,while in the successive approximation pha, switches S4are on and switches S1and S5are off.During the tracking pha,the voltage VCM is applied to the comparator stage.The voltage VCM has to be
(VREFP
Fig.10.Measured static
characteristics.
Fig.11.Measured dynamic characteristics.
large capacitors are necessary to obtain enough linearity while the resistance aris from the on resistance of the transmission gates.
The whole comparator stage consists of a fast open-loop gain stage with offt cancellation,a fast clocked comparator,and some additional logic in the SAR as well as in the control logic (e Fig.8).
When the control signal LATCH of the comparator is low,its output signals CP and CN are t to low and its positive feedback is open.With the rising clock edge,the LATCH signal is t to high,which triggers the comparator and has the effect that one of the output signals CP or CN changes to high,depending on the input voltage difference.When the high signal is detected the LATCH signal is ret to low,the bits for the DACs are t and a new charge redistribution is started.The next rising clock edge begins this procedure anew.This increas the critical time for the charge redistribution to nearly one whole clock cycle,independent from the clock duty cycle.
TABLE I K EY F
EATURES The cond clock edge is only ud to abort a decision of the comparator if its input signal difference is too small to decide within a few nanoconds.The successive approximation algo-rithm ensures that the error of a wrong decision caud by an aborted decision is always only a fraction of an LSB.This usage of the cond clock edge reduces the freedom of the clock duty cycle to the range between about 25%and 75%.
This lf-timed solution does the time partitioning itlf.When the comparator has to detect a very small voltage differ-ence,the time for the charge redistribution is longer,becau the previous one was an easy and fast decision.The subquent charge redistribution needs less time,becau an uncritical decision always follows.This correlation and the timing of the comparator are shown in Fig.9.
The combination of all tho improvements makes it possible to increa the sampling rate and to reduce the power consump-tion at the same time.
IV .I MPLEMENTATION AND M EASURED R ESULTS
The conventional 10-bit converter which was described in Section II was designed in the
0.6-m process as well,to compare the
new architecture with the old one.Both converters are noncali-brating ADCs with poly1-poly2capacitor arrays.To achieve the required linearity a special common centroid layout technique
was ud to build a 12-bit accurate capacitor array [7],[8].The greatest advantage of the new architecture is to have a higher sampling rate and lower power consumption at the same time,as shown in Table I.The sampling rate is incread by the factor 2,the power consumption is decread by the factor 1.5.This results in an overall improvement by the factor 3.Further-more the resolution is incread from 10to 12bit and the input and reference capacitances are almost the same for the 10-bit and the 12-bit ADC which is comparable with an effective re-duction of about the factor 4.The area of the new 12-bit cell is about the same as that for the old 10-bit cell.Altogether this is an effective size reduction of about one third,mainly becau the buffer as well as the blocking capacitors were removed.In Table II,typical parameters of the conventional 10-bit and the new 12-bit converter are listed.The measurements were done at the maximum conversion rate with a supply voltage of
TABLE II
webqq登陆网页M EASURED R ESULTS AT 5.0-V S
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Fig.12.
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5V and a dynamic input range
of
V ,
temperature
C,worst-ca process).The resolution was improved from 10-bit to 12-bit while the area remained roughly the same.Furthermore,the applicability of the converter in an integrated system was facilitated noticeably becau of the re-duction of the input and reference capacitance.
A CKNOWLEDGMENT
The author would like to thank G.Schatzberger,W.Meus-burger,and C.Trattler for uful discussions.
R EFERENCES
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尽其所能[8]P.O’Leary,Practical Aspects of Mixed Analogue and Digital Design,
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