专利名称：Radix-8 fixed-point FFT logic circuit
characterized by prervation of square
root-i operation
发明人：Yasunao Katayama,Kohji Takano
申请号：US13300710
青春舞动申请日：20111121
公开号：US08838661B2
公开日：
孕25周
一份牵挂20140916
专利内容由知识产权出版社提供
花词专利附图：
竞聘相信梦想的力量摘要：A system and method to reduce roundoff error of Fast Fourier transform (FFT)operation. Data which comes out as an irrational number (a square root) out of twiddle
周末好去处factors on a complex plane, included in a butterfly operation (8p) is prerved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.白色英语怎么说
申请人：Yasunao Katayama,Kohji Takano
地址：Kanagawa-ken JP,Kanagawa-ken JP
国籍：JP,JP
代理人：Jeff Tang
更多信息请下载全文后查看
