Freescale Semiconductor
Application Note
The design guidelines prented in this application note apply to products that leverage the DDR3 SDRAM IP core, and they are bad on a compilation of internal platforms designed by Freescale Semiconductor, Inc. The purpo of the guidelines is to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer.
Freescale highly recommends that the system/board designer verify all design aspects (signal integrity, electrical timings, and so on) through simulation before PCB fabrication.
Document Number:AN3940
Rev. 1, 03/2010
Contents
1.Designer Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.Termination Dissipation . . . . . . . . . . . . . . . . . . . . . . . 7
3.V REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.VTT Voltage Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.Layout Guidelines for the Signal Groups . . . . . . . . . . 8
我们的爱在赎罪
6.Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces
by Networking and Multimedia Group
Freescale Semiconductor, Inc.
Austin, TX
Designer Checklist
1Designer Checklist
In the following checklist, some of the items are phrad as question, others as requirements. In all cas, it is recommended to consider the line item and check it off in the rightmost column of Table1.
Table1. DDR3 Designer’s Checklist
Item Description Yes/No
Simulation
1.Have optimal termination values, signal topology, trace lengths been determined through simulation for each
signal group in the memory implementation? If on-die termination is ud at both the memories and the controller,
no additional termination is required for the data group.
The following unique groupings exist:
1.Data Group: MDQS(8:0), MDQS(8:0), MDM(8:0), MDQ(63:0), MECC(7:0)
2.Address/CMD Group: MBA(2:0), MA(15:0), MRAS, MCAS, MWE.
3.Control Group: MCS(3:0), MCKE(3:0), MODT(3:0)
4.Clock Group: MCK(5:0) and MCK(5:0)
The groupings assume a full 72-bit data implementation (64-bit + 8 bits of ECC). Some products may only
implement 32-bit data and may choo to have fewer MCS, MCKE, and MODT signals. Some products support
the optional MAP AR_OUT and MAP AR_ERR for registered DIMMs. In such cas, MAP AR_OUT should be
treated as part of the ADDR/CMD group and MAPAR_ERR can be treated as an asynchronous signal.
2.Does the lected termination scheme meet the AC signaling parameters (voltage levels, slew rate, and
overshoot/undershoot) across all memory chips in the design?
Termination Scheme
It is assumed that the designer is using the mainstream termination approach as found in commodity PC motherboards. Specifically, it is assumed that on-die termination is ud for the data groups and that external parallel resistors tied to VTT are ud for the Address/CMD and the control groups. Conquently, differing termination techniques may also prove valid and uful. However, they are left to the designer to validate through simulation.
3.Is the worst ca power dissipation for the termination resistors within the manufacturer’s rating for the lected
devices? See Section2, “Termination Dissipation.”
4.If resistor packs are ud, have data lanes been isolated from the other DDR3 signal groups?
Note: Becau on-die termination is the preferred method for DDR3 data signals, external resistors for the data
group should not be required. This item would only apply if the ODT feature is not ud.
5.Have V TT resistors been properly placed? The R T terminators should directly tie into the V TT island at the end of
the memory bus.
6.Is the differential terminator prent on the clock lines for discrete memory populations? (DIMM modules contain
this terminator.) Nominal range => 100–120 Ω.
7.Recommend that an optional 5pF cap be placed across each clock diff pair. If DIMM modules are ud, the cap
should be placed as cloly as possible to the DIMM connector. If discrete devices are ud, the cap should be
placed as cloly as possible to the discrete devices.
V TT Related Items
8.Has the worst ca current for the V TT plane been calculated bad on the design termination scheme? See
小说排行榜前十名Section2, “T ermination Dissipation.”
9.Can the V TT regulator support the steady state and transient current needs of the design?
Designer Checklist
Table1. DDR3 Designer’s Checklist (continued)
Item Description Yes/No 10.Has the V TT island been properly decoupled with high frequency decoupling? At least one low ESL cap, or two
standard decoupling caps for each four-pack resistor network (or every four discrete resistors) should be ud. In
addition, at least one 4.7-μF cap should be at each end of the V TT island.
Note: This recommendation is bad on a top-layer V TT surface island (lower inductance). If an internal split is
ud, more capacitors may be needed to handle the transient current demands.
11.Has the V TT island been properly decoupled with bulk decoupling? At least one bulk cap (100–220μF) capacitor
should be at each end of the island.
12.Has the V TT island been placed at the end of the memory channel and as cloly as possible to the last memory
bank? Is the V TT regulator placed in clo proximity to the island?
13.Is a wide surface trace (~150 mils) ud for the V TT island trace?
14.If a n pin is prent on the V TT regulator, is it attached in the middle of the island?
V REF
15.Is V REF routed with a wide trace? (Minimum of 20–25 mil recommended.)
16.Is V REF isolated from noisy aggressors? In addition, maintain at least a 20–25 mil clearance from V REF to other
traces. If possible, isolate V REF with adjacent ground traces.
17.Is V REF properly decoupled? Specifically, decouple the source and each destination pin with 0.1uf caps.
18.Does the V REF source track variations in V DDQ, temperature, and noi as required by the JEDEC specification?
19.Does the V REF source supply the minimal current required by the system (memories + processor)?
一个人的冒险20.If a resistor divider network is ud to generate V REF, are both resistors the same value and 1% tolerance?
Routing
21.The suggested routing order within the DDR3 interface is as follows:
1.Data address/command
2.Control
3.Clocks
4.Power
This order allows the clocks to be tuned easily to the other signal groups. It also assumes an open critical layer
图瓦卢地图
on which clocks are freely routed.
22.Global items are as follows:
•Do not route any DDR3 signals overs splits or voids.
•T races routed near the edge of a reference plane should maintain at least 30–40 mil gap to the edge of the reference plane.
•Allow no more than 1/2 of a trace width to be routed over via antipad.
23.When routing the data lanes, route the outermost (that is, longest lane first) becau this determines the amount
of trace length to add on the inner data lanes.
24.The max lead-in trace length for data/address/command signals, are not longer than 7 inches?
25.Are the clock pair assignments optimized to allow break-out of all pairs on a single critical layer?
Designer Checklist
Table1. DDR3 Designer’s Checklist (continued)
Item Description Yes/No 26.The DDR3 data bus consists of 9 data byte lanes (assuming ECC is ud). All signals within a given byte lane
should be routed on the same critical layer with the same via count.
Note: Some product implementations may only implement a 32-bit wide interface.
Byte Lane 0—MDQ(7:0), MDM(0), MDQS(0), MDQS(0)
Byte Lane 1—MDQ(15:8), MDM(1), MDQS(1), MDQS(1)
Byte Lane 2—MDQ(23:16), MDM(2), MDQS(2), MDQS(2)
Byte Lane 3—MDQ(31:24), MDM(3), MDQS(3), MDQS(3)
Byte Lane 4—MDQ(39:32), MDM(4), MDQS(4), MDQS(4)
Byte Lane 5—MDQ(47:40), MDM(5), MDQS(5), MDQS(5)
Byte Lane 6—MDQ(55:48), MDM(6), MDQS(6), MDQS(6)
Byte Lane 7—MDQ(63:56), MDM(7), MDQS(7), MDQS(7)
Byte Lane 8—MECC(7:0), MDM(8), MDQS(8), MDQS(8)
T o facilitate fan-out of the DDR3 data lanes (if needed), alternate adjacent data lanes onto different critical layers.
See Figure1 and Figure2.
Note: If the device supports ECC, Freescale highly recommends that the ur implement ECC on the initial
hardware prototypes.
27.DDR3 data group—impedance range and spacing
Option #1 (wider traces—lower trace impedance)
•Single-ended impedance = 40 Ω. The lower impedance allows traces to be slightly clor with less cross-talk.
•Utilize wider traces if stackup allows (7–8mils)
•Spacing to other data signals = 1.5x to 2.0x
•Spacing to all other non-DDR signals = 4x
Option #2 (smaller traces—higher trace impedance)
•Single-ended impedance = 50 Ω.
•Smaller trace widths (5–6mil) can be ud.
•Spacing between like signals should increa to 3x (for 5mil) or 2.5x (for 6mil) respectively
28.Check the following across all DDR3 data lanes:
•For MPC8572 and MPC8536, are all the data lanes matched to within 0.1 inch?
•For all other devices, are all the data lanes matched to within 2.0 inch?
29.Is each data lane properly trace matched to within 20 mils of its respective differential data strobe? (Assumes
highest frequency operation.)
30.When adding trace lengths to any of the DDR3 signal groups, ensure that there is at least 25 mils between
rpentine loops that are in parallel.
Designer Checklist
Table1. DDR3 Designer’s Checklist (continued)
Item Description Yes/No 31.MDQS/MDQS differential strobe routing
Note: Some product implementations may support only the single-ended version of the strobe.
•Match all gment lengths between differential pairs along the entire length of the pair. T race match the MDQS/ MDQS pair to be within 10 mils.
•Maintain constant line impedance along the routing path by maintaining the required line width and trace paration for the given stackup.
•Avoid routing differential pairs adjacent to noisy signal lines or high speed switching devices such as clock chips.
•Differential 75–95 Ω
•Diff Gap = 4–5 mils (as DQS signals are not aka pudo differential
加快的近义词Option #1 (wider traces—lower trace impedance)
•Single-ended impedance 40 Ω. The lower impedance allows traces to be slightly clor with less cross-talk.
•Utilize wider traces if stackup allows (7–8mils)
•Spacing to other data signals = 2x.
•If not routed on the same layer as its associated data, then 4x spacing
Option #2 (smaller traces—higher trace impedance)
•Single-ended impedance = 50 Ω.
•Smaller trace widths (5–6mil) can be ud.
•Spacing between like signals (other data) should increa to 3x (for 5mil) or 2.5x (for 6mil) respectively.
•Do not divide the two halves of the diff pair between layers. Route MDQS/MDQS pair on the same critical layer as its associated data lane.
32.DDR3 address/command/control group—impedance range and spacing
•Daisy chain from chip to chip. The routing should go from chip 0 to chip n, where chip 0 is the one that has the lower data bits DQ[0:7]… and chip n has the upper data bits. The daisy chain should end at the termination
resistors that are after chip n.
•With regards to physical/spacing properties
语录Option #1 (wider traces—lower trace impedance)
•Single-ended impedance = 40 Ω. The lower impedance allows traces to be slightly clor with less cross-talk.
•Utilize wider traces if stackup allows (7–8mils)
•Spacing to other like signals = 1.5x to 2.0x
•Spacing to all other non-DDR signals =3–4x
Option #2 (smaller traces—higher trace impedance)
•Single-ended impedance = 50 Ω.
•Smaller trace widths (5–6mil) can be ud.
牧羊女和扫烟囱的人•Spacing between like signals should increa to 3x (for 5mil) or 2.5x (for 6mil) respectively
•Spacing to all other non-DDR signals =3–4x
•With regards to tuning
•T une signals to 20 mil of the clock at each device.
33.DDR3 differential clocks
喜不自胜Route as diff pair. With regards to diff properties, recommendations are as follows:
•P-to-N tuning = 10 mils
•T arget single-ended impedance 40–50 Ω. The lower impedance reduces cross-talk.
•Differential 75–95 Ω
•Diff Gap = t per stackup
Option #1 (wider traces—lower trace impedance)
•Attempt to utilize wider traces if stackup allows (7–8mils)
•Spacing to other signals = 4x.
Option #2 (smaller traces—higher trace impedance)
•Single-ended impedance = 50 Ω.
•Smaller trace widths (5–6mil) can be ud.
•Spacing to other signals = 4x.
