TSV (THROUGH SILICON VIA) INTERCONNECTION ON
WAFER-ON-A-WAFER (WOW) WITH MEMS TECHNOLOGY
Koji Fujimoto1, Nobuhide Maeda2, Hideki Kitada2, Kosuke Suzuki1, Tomoji Nakamura3, and Takayuki Ohba2
1 Dai Nippon Printing Co., Ltd., Kashiwa, Japan
2The University of Tokyo, Tokyo, Japan
3Fujitsu Laboratories Ltd., Atsugi, Japan
Tel:+81-4-7134-3005,Fax:+81-4-7133-2540,E-mail:********************.co.jp
ABSTRACT
大圆脸发型
The fabrication of WOW (wafer-on-a-wafer) with MEMS technology has been developed. A wafer was thinned and stacked on a ba wafer. After the TSVs were patterned on the thinned wafer, they were filled by Cu for interconnection. The wafers were bonded with benzocylcobutene (BCB, CYCLOTENE T
M) as an adhesive material. The BCB layer was also acted as a dielectric layer between top and bottom silicon wafers. The TSVs were created by DRIE (Deep Reactive Ion Etching) and filled by Cu electroplating. This paper describes that thinned Si wafers down to 20µm were stacked on a ba wafer with TSVs interconnection filled by Cu. The thinned wafers were stacked up to ven. The electrical characteristics were measured by daisy-pattern including 243 TSVs filled by Cu and the stress simulation for TSV was also shown.
KEYWORDS
WoW, BCB, CYCLOTENE, TSV, Cu interconnection, wafer-level packaging, stacking.
华南理工大学是211还是985INTRODUCTION
In recent years, the scale of miconductor devices comes to the limit in the points of lithography, heat value, and so on. Three-dimensional interconnection by TSV between miconductor devices is expected to solve the issues. The TSV interconnection filled by Cu has been rearched and reported in published papers [1-5]. However, the TSV technology is still on the stage of rearch and has many points to improve in the view of fabrication process.
The key issues for three-dimensional interconnection are 1) stacking on wafer level, 2) TSVs with low aspect ratio, 3) via last formation, and 4) bump-less contact. The conventional stacking methods are chip to chip or wafer to chip stacking. The methods have disadvantages for through-put and process cost. Therefore, wafer-level stacking has to be required. The 2) low aspect ratio of TSVs reduces process difficulty and leads to short process time and high yield rate. The 3) via-last formation decreas fabrication damage for the miconductor devices. Finally, the 4) bump-less contact removes the problems of bump contact, for instance, tilting of the stacked chip, voids and so on.
This paper shows the solution for the issues mentioned above. The wafers were stacked on wafer-level with an adhesive layer of benzocylcobutene (BCB, CYCLOTENE TM). The stacking with the BCB makes it possible to bump-less contact. The stacked Si wafers on a ba wafer were thinned by back-grind to reduce the aspect ratio of TSVs. By repeating all the same process for stacking and TSV formation filled by Cu, the veral thinned wafers were stacked and interconnected with the ba wafer, leading to high-density 3D packaging.
The mask design includes daisy-chain patterns on an
8inch wafer as shown in Figure1. The three dimensional interconnection technology has been developed for miconductor devices mainly, however, the technology is very important for MEMS products as well. The electrical interconnection between MEMS devices and their package often results in making chip size large. Therefore, the stacking method with the BCB on wafer level and interconnection by Cu filled TSV meet the requirements for MEMS products and offers flexible packaging method with process compatibility of MEMS.
DESIGN AND FABRICATION PROCESS
Figure2 shows the process flow. A wafer, which was patterned by Au/TiN/Ti pads on SiN/SiO2 dielectric layers, was temporarily bonded to a glass wafer. The thickness of the layers was 130nm for Au, 50nm for Ti and TiN. The pattern size of the Au/TiN/Ti layer was 62μ
护士的工作内容
m long and Figure1. Layout of TSV pattern
62μm wide. The thickness of the SiN and SiO2 layers were 200nm and 500nm respectively. The S
iO2 layer was thermally oxidized and the SiN layer was deposited by LP-CVD (Low Pressure Chemical Vapor Deposition). The patterned wafer was thinned down to 20μm thickness by back grind in DISCO corporation. The thinning process is shown in Figure3. The thinned wafer was stacked on a ba wafer with an adhesive layer of BCB [6]. The thickness of the BCB layer was approximately 5 μm. Therefore, the total thickness of one layer was 25μm including the thinned Si and the BCB layer. The ba wafer was also patterned by the same process as the thinned wafer without the back grind and the temporary bonding. The pattern of the ba wafer was 142μm long and 62μm wide of the Au/TiN/Ti pad. The thinned wafer was aligned with the ba wafer with both-side alignment. After the glass is parated by wet process, photo-resist for the TSV layout with daisy chain was patterned on surface of the bonded wafer.
站立推墙
No plasma
Wafer
Suport glass: for thinned wafer handling
No vacuum No chemical
The Au/TiN/Ti and SiN/SiO2 layers were etched by wet process and by RIE (Reactive Ion Etching), r
espectively. The silicon layer was procesd by DRIE for TSVs (shown in Figure4) with small scallops of 100nm P-V. The diameter of the TSV holes was 30μm. After the BCB layer was etched by RIE with oxygen plasma [7], a dielectric layer of SiN with 1μm thickness was deposited by PE-CVD (Plasma Enhanced Chemical Vapor Deposition). The SiN layer was etched by anisotropic RIE without any masks, remaining the dielectric layer on the side wall and removing the top and the bottom, as shown in Figure5. Following the sputtering of a ed layer (Cu: 500nm, TiN: 50nm, Ti: 50nm), dry film resist (DFR) was patterned and the TSVs were filled by Cu electroplating. The top of Cu on TSVs was flattened by Surface planar TM of DISCO Corporation in Figure6.
Figure4. TSV side wall
Fugure3. Thinning Process
Glass Back grind
Figure2. Process Flow
of SiN
TSV filled by Cu & Planarized
A. Back Grind
B. BCB Bonding
C. TSV
D. Side-wall Dielectric film
E. Cu Electroplating & Surface Planarization
μm thick.
Rough surface
Finally, the DFR was removed by wet process. By repeating the same process, veral layers were stacked on top of the ba wafer. It was demonstrated that total ven thinned wafers were stacked with Cu interconnections filled in TSVs (Figure7). After stacking veral thinned Si with the BCB, the top side was patterned with photo-resist, following Ni and Au electroplating. The Au/Ni pads were acted as top electrodes for the daisy chain. The thickness of the Ni and Au were 1μm and 0.5μm respectively.
Figure7. Seven wafers stacked on a wafer with TSVs
RESULTS AND DISCUSSIONS
The fabricated TSVs filled by Cu of 2 wafers stacked on the ba wafer are shown in Figure 8. It was shown that the TSVs were filled by Cu and interconnected between top and bottom Si wafers without
the voids. There were also no voids in the BCB layer between the thinned Si layers. It is turned out that the BCB is applicable for wafer bond. It is well-known that BCB has advantages of low-temperature curing, flatness, and the low dielectric constant. Therefore, BCB layer works well for not only dielectrics but also permanent adhesive bond.
The X-ray CT image is also shown in Figure 8. It was indicated that TSVs were filled by Cu uniformly.
The resistance distribution of the daisy chain with 243 TSVs was measured after pad metal formation (Figure9). The medium value was the single TSV was 0.2 ohm, which almost corresponds to the theoretical value. It was demonstrated that the top and the bottom wafers were well-connected by the TSVs filled with Cu.
Figure5. Side wall Dielectrics (SiN)
Si
Si
墙纸图片大全SiN
SiN
Fugure6. Surface Plain Process
TSVs filled by Cu
Figure8. Cross ction and X-ray CT
BCB
Figure9. Resistance distribution
The result of stress simulation is shown in Figure10. The simulation shows the stress comparison between the thick and thinned wafers. The result indicated that the thinned wafer suffered lower stress than the thick. Therefore, the thin wafer is suitable for stacking with Cu TSV interconnection comparing with the thick.
CONCLUSION
The TSVs interconnection on WOW was developed with MEMS technology. Several wafers up to ven were stacked with BCB. The electrical characteristics were measured and its result was appropriate. It was demonstrated of the bump-less stacking on wafer level and TVS interconnections filled by Cu.
The process shown in the paper is so uful that it is applicable to various MEMS applications like μTAS, nsors, RF and so on. They are often required to al in vacuum and interconnect between inner pads and outer pads. In addition, the size for packaging has to be as small as possible. The key technologies for small packaging are handling for thinner wafer and wafer-level bonding with metal interconnections of bump-less. The solution for the key technologies was shown in the paper. In the future, the vacuum al by BCB will be rearched and reported. ACKNOWLEDGEMENTS
We would like to thank DISCO Corporation for thinning wafers, NISSAN Chemical and SUMITOMO 3M for wafer bond. This work is carried out in the WOW alliance program.
REFERENCES
[1] Henry, D. et al., Electronic Components and Technology Conference, Electronic Components and Technology Conference, 2008. ECTC 2008. 58th, pp. 556 - 562.
[2] Henry, D. et al., Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th, pp. 215 - 221.
试纸条
[3] Rimskog, Magnus, Electronic Manufacturing Technology Symposium, 2007. IEMT '07. 32nd IEEE/CPMT International Publication Date: 3-5 Oct. 2007, pp286 - 289
宣誓口号[4] Morrow, P.R., et al, Electron Device Letters, IEEE, May 2006 Volume: 27, Issue: 5, pp. 335 - 337.
[5] Ramm, P., et al, Electronic Components and Technology Conference, 2008. ECTC 2008. 58th, May 2008, pp. 841 - 846.
我的伙伴[6] Oberhammer, J., et al, Sensors and Actuators, A105, 2003, pp.297-304.
[7] Chinoy, P. B., IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part C, Vol.20, No.3, July 1997, pp.199-206.
CONTACT
K. Fujimoto,
tel:+81-4-7134-3005;********************.co.jp
Figure10. Stress simulation of TSV filled by Cu between thin and thick wafer
