Dual Channel, High CMR,High Speed, TTL Compatible Optocouplers
8 Pin DIP and SOIC-8Technical Data
HCPL-2630 HCPL-0630HCPL-2631 HCPL-0631HCPL-4661 H CPL-0661
Features
• Available in 8 Pin DIP and SOIC-8空调外机不工作
• Internal Shield for High Common Mode Rejection (CMR)
细微之处见真情HCPL-2631/0631: 10,000 V/µs @ V CM = 50 V
HCPL-4661/0661: 15,000 V/µs @ V CM = 1000 V
• High Density Packaging • Low Input Current Capability: 5 mA • High Speed: 10 MBd • LSTTL and TTL Compatible
• Guaranteed AC and DC Performance Over
无论还是造句
Temperature: -40°C to 85°C • Recognized Under the Component Program of UL1577 (File No. E55361)for Dielectric Withstand Proof Test Voltages of 2500Vrms, 1 Minute
• 5000 Vrms, 1 Minute
(Option 020) (HCPL-2630/2631/4661)
• CSA Approved Under Component Acceptance Notice No. 5 (File No. CA 88324) (HCPL-2630/2631/4661)
• Hermetic Equivalent Device Available (HCPL-5630/31)
• Surface Mount Gull Wing Option Available for 8 Pin DIP (Option 300)
Outline Drawing - 8 Pin DIP俬怎么读
CAUTION: The small junction sizes inherent to the design of this bipolar component increa the component's susceptibility to damage from electrostatic discharge (ESD). It is advid that normal static precautions be taken in handling and asmbly of this component to prevent damage and/or degradation which may be induced by ESD.
DIMENSIONS IN MILLIMETERS AND (INCHES).
V V O1O2
ANODE CATHODE CATHODE ANODE H
Outline Drawing - SO-8 Outline Drawing - Option 300
0.51 ±
(0.020 ±
0.25
DIMENSIONS IN mm (IN.)
TOLERANCES: xx.xx = 0.01
< = 0.005
(unless otherwi specified)
LEAD COPLANARITY任好
MAXIMUM: 0.102 (0.004)
[2][5]
LEAD COPLANARITY ±
OF THE PACKAGE
DIMENSIONS IN MILLIMETERS AND (INCHES).
Description
The dual channel devices are optically coupled logic gates
宝宝嘴唇干裂出血怎么办that combine GaAsP light emitting diodes and integrated high gain photodetectors. The photons are collected in the detector by a photodiode and the current is amplified by a high gain linear amplifier that drives a Schottky clamped open collector output transistor. Each circuit is temperature, current and voltage compensated. The internal shield provides a guaranteed common mode transient immunity specification of 5000 V/µs for the HCPL-2631/0631, and 10,000 V/µs for the HCPL-4661/0661.
The dual channel optocouplers are available in an 8 Pin DIP and in an industry standard SOIC-8 package. The following is a cross reference table listing the 8 Pin DIP part number and the electrically equivalent
SOIC-8 part number.
SOIC-8
8 Pin DIP Package
HCPL-2630HCPL-0630
HCPL-2631HCPL-0631
HCPL-4661HCPL-0661
The SOIC-8 does not require “through holes” in a PCB. This package occupies approximately one-third the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount process.
The unique design provides maximum ac and dc circuit isolation while achieving LSTTL and TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40°C to +85°C. The dual channel design
minimizes PCB space.
The devices are recommended
for high speed logic interfacing,
input/output buffering, and for
u as line receivers in environ-
ments that conventional line
receivers cannot tolerate. They
can be ud for the digital
programming of machine
control systems, motors and
floating power supplies. The
internal shield makes the
HCPL-2631/0631/4661/0661
ideal for u in extremely high
ground or induced noi
environments.
台球加塞Applications
• Isolation of High Speed
Logic Systems
• Microprocessor System
Interfaces
• Isolated Line Receiver
• Computer-Peripheral
Interfaces
• Ground Loop Elimination
• Digital Isolation for A/D,
D/A Conversion
• Power Transistor Isolation
in Motor Drives Schematic
GND
O2
V
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 1).
V CC
O1
V
Recommended Operation Conditions
Parameter Symbol Min.Max.Units Input Current, Low Level Each Channel I FL *0250µA Input Current, High Level Each Channel I FH 515mA Supply Voltage, Output V CC 4.5
5.5V Fan Out (@ R L = 1 k Ω)Each Channel N 5TTL Loads
Output Pull-up Resistor R L 330 4 k ΩOperating Temperature
T A
-4085
°C
*The off condition can also be guaranteed by ensuring that V FL ≤ 0.8 volts.
Absolute Maximum Ratings
(No Derating Required up to 85°C)
-55°C to +125°C -40°C to +85°C Lead Solder Temperature (8 Pin DIP)..........................260°C for 10 s
(1.6 mm below ating plane)
Average Forward Input Current
(each channel, See note 2)......................................................15 mA Rever Input Voltage (each ch
annel).......................................... 5 V Supply Voltage – V CC (1 Minute Maximum)................................ 7 V Output Collector Current – I O (each channel)..........................50 mA Output Collector Voltage – V O (each channel)**...........................7 V Output Collector Power Dissipation (each channel)...........60 mW [17]Infrared and Vapor Pha Reflow
Temperature (SOIC-8 & Option #300)............See Thermal Profile
**Selection for higher output voltages up to 20 V is available.
Maximum Solder Reflow Thermal Profile. (Note: U of non-chlorine activated fluxes is highly recommended.)
Thermal Profile
2400
TIME – MINUTES
T E M P E R A T U R E – °C
220200180160140120100806040200
2601
2
3
4
5
6
7
8
9
10
11
12
Electrical Characteristics
Over recommended temperature (T A = -40°C to +85°C) unless otherwi specified. (See note 1.)
*All typical values are at V CC = 5 V, T A = 25°C.**For HCPL-2630/2631/4661 only.***For HCPL-0630/0631/0661 only.
Parameter Symbol Device
Min.Typ.*Max.
Units Test Conditions Fig.Note Propagation Delay 75
ns
T A = 25°C
Time to High t PLH
20
48
7, 8, 9
3, 6
Output Level 100ns Propagation Delay 75
ns
T A = 25°C
Time to Low t PHL 25
50
7, 8, 93, 7Output Level 100
ns R L = 350 ΩPul Width |t PHL -t PLH |
3.5
35ns C L = 15 pF
10
13Distortion Propagation Delay t PSK 40
ns 13,14Skew
Output Ri Time t r 24ns 113(10-90%)
Output Fall Time t f
10ns
11
3
(90-10%)Common Mode HCPL-2630/0630
10,000
V CM = 10 V V O(MIN) = 2 V,Transient R L = 350 Ω,Immunity at |CM H |
HCPL-2631/0631
5,00010,000
V/µs
V CM = 50 V I F = 0 mA,12
3, 8,High Output T A = 25°C 10
Level HCPL-4661/066110,00015,000V CM = 1000 V Common Mode HCPL-2630/0630
10,000
V CM = 10 V
V O(MAX) = 0.8 V ,Transient R L = 350 Ω,Immunity at |CM L |
HCPL-2631/0631
5,00010,000
V/µs
V CM = 50 V I F = 7.5 mA 12
3, 9,Low Output T A = 25°C
10
Level
HCPL-4661/066110,00015,000
V CM = 1000 V
Switching Specifications
Over recommended temperature (T A = -40°C to +85°C), V CC = 5 V, I F = 7.5 mA, unless otherwi specified.
*All typical values are at V CC = 5 V, T A = 25°C.
Notes:
1.Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler. Total lead length between both ends of the capacitor and the isolator pins should
not exceed 10 mm.
2.Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pul width, provided average current does not exceed 15 mA.
校园文化建设方案3. Each channel.
4. Measured between pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
5. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
6. The t PLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pul to the 1.5 V point on the rising edge of the output pul.
7. The t PHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pul to the 1.5 V point on the falling edge of the output pul.
8. CM H is the maximum tolerable rate of ri of the common mode voltage to assure that the output will remain in a high logic state (i.e., V OUT > 2.0 V).
9. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V OUT < 0.8 V).
10.For sinusoidal voltages, (|dV CM |/dt)max = πf CM V CM (p-p).
11.As illustrated in Figure 15 the V CC and GND traces can be located between the input and the output leads to provide
additional noi immunity at the compromi of insulation capability.
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V RMS for 1 cond
(Leakage detection current limit, I I-O ≤ 5 µA).
13. See application ction; “Propagation Delay, Pul-Width Distortion and Propagation Delay Skew” for more information.14. t PSK is equal to the worst ca difference in t PHL and/or t PLH that will be en between units at any given temperature within
the operating condition range.
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V RMS for 1 cond
(Leakage detection current limit, I I-O ≤ 5 µA). This option is valid for HCPL-2630/2631/4661 only.
16. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together.17. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
