Ultrafast 3.3 V/5 V
猫咪图片
Single-Supply SiGe Comparators
ADCMP572/ADCMP573 Rev.0
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However, no responsibility is assumed by Analog Devices for its u, nor for any
infringements of patents or other rights of third parties that may result from its u. Specifications subject to change without notice. No licen is granted by implication or otherwi under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329. Fax: 781.461.3113© 2005 Analog Devices, Inc. All rights rerved.
FEATURES
3.3 V/5.2 V single-supply operation
150 ps propagation delay
15 ps overdrive and slew rate dispersion
8 GHz equivalent input ri time bandwidth
80 ps minimum pul width
35 ps typical output ri/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
On-chip terminations at both input pins
Robust inputs with no output pha reversal
Resistor-programmable hysteresis
Differential latch control
Extended industrial −40°C to +125°C temperature range
APPLICATIONS
Clock and data signal restoration and level shifting Automatic test equipment (ATE)
High speed instrumentation
Pul spectroscopy
taste的过去式Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
FUNCTIONAL BLOCK DIAGRAM
V P
V TP
V TN
V N
4
4
9
-
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5
Figure 1.
GENERAL DESCRIPTION
The ADCMP572 and ADCMP573 are ultrafast comparators fabricated on Analog Devices’ proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP572 features CML output drivers and latch inputs, and the ADCMP573 features reduced swing PECL (RSPECL) output drivers and latch inputs.
虚拟主机空间
Both devices offer 150 ps propagation delay and 80 ps minimum pul width for 10 Gbps operation with 200 fs rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 15 ps.
A flexible power supply scheme allows both devices to operate with a single 3.3 V positive supply and a −0.2 V to +1.2 V input signal range or with split input/output supplies to support a wider −0.2 V to +3.2 V input signal range and an independent range of output levels. 50 Ω on-chip termination resistors are provided at both inputs with the optional capability to be left open (on an individual pin
basis) for applications requiring high impedance inputs.
The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to between 3.3 V to 5.2 V. The RSPECL output stage is designed to drive 400 mV into
梦见蛇是什么预兆50 Ω terminated to V CCO − 2 V and is compatible with veral commonly ud PECL logic families. The comparator input stage offers robust protection against large input overdrive, and the outputs do not pha rever when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided.
The ADCMP572 and ADCMP573 are available in a 16-lead LFCSP package and have been characterized over an extended industrial temperature range of −40°C to +125°C.
ADCMP572/ADCMP573
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
.3 Absolute
..................................................5 5 5 Pin Configuration and 6 Typical 7 9 Power/Ground Layout 9 CML/RSPECL 9 Using/Disabling the 9 Optimizing High .10 Comparator Propagation 10 11 Minimum Input Slew .11 Typical .12 13 14 Ordering Guide.. (14)
REVISION HISTORY
4/05—Revision 0: Initial Version
ADCMP572/ADCMP573
Rev. 0 | Page 3 of 16
ELECTRICAL CHARACTERISTICS
V CCI = V CCO = 3.3 V , T A = −40°C to +125°C, typical at T A = +25°C, unless otherwi noted. Table 1.
Parameter Symbol Conditions M in Typ M ax Unit DC INPUT C H
ARACTERISTICS Input Voltage Range V P , V N V CCI = 3.3 V, V CCO = 3.3 V −0.2 +1.2 V V CCI = 5.2 V, V CCO = 3.3 V −0.2 +3.1 V Input Differential Voltage −1.2 +1.2 V Input Offt Voltage V OS −5.0 ±2.0 +5.0 mV Offt Voltage Tempco ∆V OS /dT 10.0 µV/°C
Input Bias Current I P , I N Open termination −50.0 −25.0 0.0 µA Input Bias Current Tempco 50.0 nA/°C Input Offt Current ±2.0 µA Input Impedance 50 Ω Input Resistance, Differential Open termination 50 kΩ Input Resistance, Common-Mode Open termination 500 kΩ Active Gain A V 54 dB V CCI = 3.3 V, V CCO = 3.3 V, V CM = 0.0 V to 1.0 V
65 dB
Common-Mode Rejection CMRR V CCI = 5.2 V, V CCO = 3.3 V, V CM = 0.0 V to 3.0 V
65 dB Power Supply Rejection—V CCI PSR VCCI V CCI = 3.3 V ± 5%, V CCO = 3.3 V 74 dB
ysteresis R HYS = ∞ ±1 mV LATC H ENABLE C H
ARACTERISTICS
ADCMP572 Latch Enable Input Range 2.8 V CCO + 0.2 V Latch Enable Input Differential 0.2 0.4 0.5 V Latch Setup Time t S V OD = 100 mV 15 ps Latch Hold Time t H V OD = 100 mV 5 ps ADCMP573 Latch Enable Input Range 1.8 V CCO − 0.6 V Latch Enable Input Differential 0.2 0.4 0.5 V Latch Setup Time t S V OD = 100 mV 90 ps Latch Hold Time t H V OD = 100 mV 100 ps Latch Enable Input Impedance 50.0 Ω Latch to Output Delay t PLOH, t PLOL V OD = 100 mV 150 ps Latch Minimum Pul Width t PL V OD = 100 mV 100 ps DC OUTPUT C H
ARACTERISTICS ADCMP572 (CML) Output Impedance Z OUT −8 mA < I OUT < 8 mA 50.0 Ω Output Voltage High Level V OH 50 Ω terminate to V CCO V CCO − 0.10 V CCO − 0.05 V CCO V Output Voltage Low Level V OL 50 Ω terminate to V CCO V CCO − 0.60 V CCO − 0.45 V CCO − 0.30 V Output Voltage Differential 50 Ω terminate to V CCO 300 375 450 mV ADCMP573 (RSPECL) Output Voltage High −40°C V OH 50 Ω terminate to V CCO − 2.0 V CCO − 1.14 V C
CO − 1.02 V CCO − 0.90 V Output Voltage High +25°C V OH 50 Ω terminate to V CCO − 2.0 V CCO − 1.10 V CCO − 0.98 V CCO − 0.86 V Output Voltage High +125°C V OH 50 Ω terminate to V CCO − 2.0 V CCO − 1.04 V CCO − 0.92 V CCO − 0.80 V Output Voltage Low −40°C V OL 50 Ω terminate to V CCO − 2.0 V CCO − 1.54 V CCO − 1.39 V CCO − 1.24 V Output Voltage Low +25°C V OL 50 Ω terminate to V CCO − 2.0 V CCO − 1.50 V CCO − 1.35 V CCO − 1.20 V Output Voltage Low +125°C V OL 50 Ω terminate to V CCO − 2.0 V CCO − 1.44 V CCO − 1.29 V CCO − 1.14 V Output Voltage Differential 50 Ω terminate to V CCO − 2.0 300 375 450 mV
ADCMP572/ADCMP573
Rev. 0 | Page 4 of 16
Parameter Symbol Conditions M in Typ M ax Unit AC PERFORMANCE Propagation Delay t PD V CCI = 3.3 V, V OD = 200 mV 150 ps V CCI = 3.3 V, V OD = 20 mV 165 ps V CCI = 5.2 V, V OD = 200 mV 145 ps Propagation Delay Tempco ∆t PD /dT 0.5 ps/°C
Prop Delay Skew—Rising Transition
to Falling Transition V OD = 200 mV, 5 V/ns 10 ps 50 mV < V OD < 0.2 V, 5 V/ns 15 ps
创意素描图片
Overdrive Dispersion 10 mV < V OD < 0.2 V, 5 V/ns 15 ps
Slew Rate Dispersion 2 V/ns to 10 V/ns, 250 mV OD 15 ps Pul Width Dispersion 100 ps to 5 ns, 250 mV OD 5 ps V CCI = 3.3 V, 1 V/ns, 250 mV OD 5 10% – 90% Duty Cycle Dispersion V CCI = 5.2 V, 1 V/ns, 250 mV OD 10
ps
Common-Mode Dispersion V OD = 0.2V, 0.0 V < V CM < 2.9 V 5 ps/V
Equivalent Input Bandwidth 1
BW EQ 0.0 V to 250 mV input
t R = t F = 17 ps, 20/80
8.0 G H
z Toggle Rate >50% Output Swing 12.5 Gbps
Deterministic Jitter DJ V OD = 200 mV, 5 V/ns,
PRBS 31
− 1 NRZ, 4 Gbps
10 ps V OD = 200 mV, 5 V/ns,
PRBS 31
− 1 NRZ, 10 Gbps
20 ps RMS Random Jitter RJ V OD = 200 mV, 5 V/ns, 1.25 GHz 0.2 ps Minimum Pul Width PW MIN ∆t PD /∆PW < 5 ps, 200 mV OD 100 ps PW MIN ∆t PD /∆PW < 10 ps, 200 mV OD 80 ps Ri Time t R 20/80 35 ps Fall Time t F 20/80 35 ps POWER SUPPLY
Input Supply Voltage Range V CCI 3.1 5.4 V
Output Supply Voltage Range V CCO 3.1 5.4 V Positive Supply Differential V CCI −V CCO −0.2 +2.3 V ADCMP572 (CML) V CCI = 3.3 V, V CCO = 3.3 V,
terminate 50 Ω to V CCO
44 52 Positive Supply Current I VCCI + I VCCO V CCI = 5.2 V, V CCO = 5.2 V,
terminate 50 Ω to V CCO
44 52 mA V CCI = 3.3 V, V CCO = 3.3 V,
terminate 50 Ω to V CCO
140 165 Device Power Dissipation P D V CCI = 5.2 V, V CCO = 5.2 V,
terminate 50 Ω to V CCO
形容自信的成语
230 265 mW ADCMP573 (RSPECL) V CCI = 3.3 V, V CCO = 3.3 V,
50 Ω to V CCO − 2 V
62 80 Positive Supply Current I VCCI + I VCCO V CCI = 5.2 V, V CCO = 5.2 V,
50 Ω to V CCO − 2V
64 80 mA V CCI = 3.3 V, V CCO = 3.3 V,
50 Ω to V CCO − 2 V
110 160 Device Power Dissipation P D V CCI = 5.2 V, V CCO = 5.2 V,
50 Ω to V CCO − 2 V
146 230 mW 1
且行且珍惜Equivalent input bandwidth assumes a simple first-order respon and is calculated with the following formula: BW EQ = 0.22/√(tr COMP 2−tr IN 2), where tr IN is the 20/80 transition time of a quasi-Gaussian signal applied to the comparator input, and tr COMP is the effective transition time digitized by the comparator.
ADCMP572/ADCMP573
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating SUPPLY VOLTAGE Input Supply Voltage (V CCI to GND) −0.5 V to +6.0 V Output Supply Voltage (V CCO to GND)
−0.5 V to +6.0 V Positive Supply Differential
(V CCI − V CCO ) −0.5 V to +3.5 V INPUT VOLTAGE
Input Voltage −0.5 V to V CCI + 0.5 V
Differential Input Voltage ±(V CCI + 0.5 V) Input Voltage, Latch Enable −0.5 V to V CCO + 0.5 V HYSTERESIS CONTROL PIN Applied Voltage (HYS to GND) −0.5 V to +1.5 V Maximum Input/Output Current ±1 mA OUTPUT CURRENT ADCMP572 (CML) ±20 mA ADCMP573 (RSPECL) −35 mA
TEMPERATURE Operating Temperature, Ambient −40°C to +125°C Operating Temperature, Junction +150°C Storage Temperature Range −65°C to +150°C
Stress above tho listed under Absolute Maximum Ratings may
cau permanent damage to the device. This is a stress rating only and functional operation of the device at the or any other
conditions above tho indicated in the operational ction of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
THERMAL CONSIDERATIONS The ADCMP572/ADCMP573 LFCSP 16-lead package has a θJA (junction-to-ambient thermal resistance) of 70°C/W in still air.
ESD CAUTION
ESD (electrostatic discharge) nsitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ADCMP572/ADCMP573
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04409-026
V C C O /V V V N V TN V C C I
G N D
H Y S
G N D
Figure 2. ADCMP572/ADCMP573 Pin Configuration
H
